Continuous improvement in terms of device scaling has been made in order to follow Moore’s law. Transition from planar structure into Fin-type Field Effect transistor (FinFET) was incorporated so as to obtain higher drive current and lower leakage. To further enhance the electrical properties, introduction of high mobility channel material in P-FET [1], silicon germanium (SiGe), was utilized, while maintaining silicon (Si) in N-FET. This brought up new challenges that are related to not only etch controllability between silicon and silicon germanium, but also interface quality on SiGe channel.

In this presentation, we will discuss the etching challenge in the dual channel fin application. In the fabrication scheme, Si and SiGe need to be etched simultaneously, which requires etched rate controllability between the two materials. However, SiGe etch rate is higher than Si under halogen chemistries. In this investigation, we developed a novel plasma process that controls the etching characteristics (i.e., higher Si etch rate than SiGe) [2], leading to Si-SiGe etched amount control. We will reveal the etch mechanism of the plasma process utilizing surface analysis and ab-initio calculation.

In addition to the etch control, interface condition between gate oxide and SiGe channel is also critical. Sub-threshold can be improved by reducing interface trap density at the interface [3], which can be achieved by obtaining a Si-rich surface. There are a few conventional methods that can achieve a Si-rich surface on SiGe such as atomic layer deposition of Si cap over SiGe [4] and GeOx scavenging [5]. All of these require high temperature processes that cause issues such as atomic diffusion and strain relaxation. In this investigation, we will introduce a plasma treatment at room temperature that creates Si-rich surface. We investigated the mechanism of the surface modification into a Si-rich surface on SiGe under the plasma treatment [6]. We will also present how this has an impact on reducing interface trap density in terms of electrical performance.

[1]. O. Weber et. al., IEDM Tech. Dig., p.719, 2007

[2]. Y. Ishii et. al., Jpn. J. Appl. Phys. 57, 06JC04 (2018)

[3]. C. H. Lee et. al., IEDM Tech. Dig., p.31.1.1., 2016

[4]. H. Mertens, et al., VLSI Tech. Dig., p.58, 2014

[5]. C.H. Lee, et. al., VLSI Tech. Dig., p. 36, 2016

[6]. Y. Ishii, et. al., IEEE J. Electron Devices Soc. 7, 1277 (2019)

Tantalum nitride (TaN) is widely used as a crucial component of diffusion barriers within the back-end-of-the-line (BEOL) because of its strong dielectric adhesion and ability to scale low in-plane resistivity and diffusion-blocking capability to sub-5 nm thicknesses. In order to create the BEOL interconnect superstructure, a cyclical process of conductor and liner deposition and etching, followed by dielectric capping must be completed. In this paper, we will explore the use of inductively-coupled plasma (ICP) discharges containing NF₃/Ar, NF₃/O₂/Ar, and NF₃/SiCl₄/Ar mixtures for the isotropic, dry etching of TaN; relying on radically-based etch, without non-selective ion bombardment. The aforementioned radically-based process is sensitive to chamber wall condition during the etching process; therefore, we considered that such methods often employ wall coatings in order to achieve superior etch uniformity and wafer-to-wafer reproducibility. This process is outlined in Figure 1; comparing the process utilizing coating and without utilizing coating. PATH A includes chamber conditioning without coating followed by the etching of the sample wafer, while PATH B includes the application of coating prior to sample wafer processing. The mechanism of SiCl₄ and O₂ PECVD of SiO₂ has been extensively studied, while the impact of the coating itself on metal and metal nitride etching has not been so well explored. The aforementioned dry-etching chemistries for the removal of TaN are compared with and without using a SiCl₄/O₂ chamber coating: comparing the etching process of the TaN film and etch selectivity to polycrystalline silicon and silicon dioxide. In-situ optical emission spectroscopy is utilized to find that the SiCl₄/O₂ chamber coating reacts with the ICP discharge to modify relative species densities when compared to a discharge without the chamber coating applied. Furthermore, modification does not only occur within the discharge, but at the film surface, where we use spectroscopic ellipsometry (SE) to find the etching selectivity of the TaN film is significantly changed with respect to the polycrystalline silicon and silicon oxide upon coating application. O₂ and SiCl₄ are separately added directly to the plasma discharge in order to characterize the effect of coating constituent gases and to ascertain if a similar affect to coating addition could be attained with direct addition of O₂ or SiCl₄ to the discharge. X-ray photoelectron ellipsometry is utilized in order corroborate SE findings, but to also give an idea of the fluorine-based etching pathway the TaN undergoes towards achieving full removal.

Etching of trenches and holes into low-k dielectrics is an indispensable process in very-large-scale integration (VLSI) applications. As the critical dimension (CD) size shrinks aggressively with the advancement of technology nodes, the same etch amount (EA) leads to significantly increased aspect ratio (AR, calculated by EA/CD). In this work, we use SiCN as an exemplary low-k dielectric to investigate the effect of AR in isotropic etch processes where F-containing neutrals are the dominant etchant and the effects from ions are minimized. Blanket SiCN films and Si shadow mask were used to form a testing structure with which AR ranging from 0:1 to 70:1 can be evaluated. The etch amount of SiCN materials and their refractive index were evaluated using Spectroscopic ellipsometry (SE). The surface composition pre- and post-etch processes were examined by X-ray photoelectron spectroscopy (XPS), and Fourier transform infrared spectroscopy (FTIR) at various ARs. We found that the etch rate and surface composition inside the shadow mask are dramatically different from those outside, which reflects the effect of ions on SiCN etching. With higher AR, the etch rate of SiCN reduces whereas the surface composition of the etched SiCN film shows the formation of F-containing etch byproduct concentrated in the AR range between 15:1 and 45:1. The etch byproduct shows a characteristic XPS N1s peak at 403.8 eV, a Si2p peak at 105.1 eV, and a large amount of Fluorine. The accumulation such byproduct in this particular AR range could be resulted from the transport property of neutral-reactants from plasma and the lack of ion bombardment.

Since IBM introduced Cu in 1997, the scaling of these interconnects has been relentless for more than two decades. Hundreds of miles of wiring are now deployed in a mindboggling small footprint for the most advanced computer chips, completing the electronic network for billions of transistors. Plasma etch has been and continues to be one of the essential process steps responsible for interconnect scaling. This review starts with some personal experiences as a young engineer, shortly after graduating in the field of plasma etch and surface science. Science and engineering are very different domains. Both are key for advancing and developing new technologies. In case of plasma etch engineering, one must understand the other processes and their constraints, both up- and down-stream in the manufacturing flow. Problems or challenges are rarely confined to a single process or sector. An example of isolated via etch-stop in a low-k dielectric will illustrate how very different engineering can be from science, and an interesting outlook for students and future engineers who are primarily focusing on science now. The review then continues through the past two decades, highlighting some of the key engineering innovations together with the plasma etch processes that enabled them, including patterning solutions for EUV and multi-layer. Finally, there are the future opportunities of interconnect scaling, arguably even more exciting than the past!

The ability to etch metals in a controlled manner has potential applications at the forefront of advanced interconnect for semiconductor scaling. In this study, the authors evaluate Ru patterning and investigate in depth Reactive Ion Etching (RIE) mechanisms of Ru film in O2/Cl2/CH4 plasma. The etch rate; profile control and mask selectivity of Ru are examined as a function of Cl2/O2 gas ratio; passivation gas CH4 addition and bias power applied. By tuning polymerization, the authors achieve 90º Ru sidewall angle. The impact of various plasma parameters on structural and electrical performance are evaluated using a 300mm Transformer Coupled Plasma (TCP) RIE chamber. The plasma-material interaction is also studied with respect to masking materials. Each of these conditions are evaluated at aggressive critical dimensions to determine the impact of reduced feature size on the ability to anisotropically etch metal structures.