AVS2010 Session PS+MN-WeM: Plasma Processing for 3D Integration, TSV, and MEMS

Deep reactive ion etching (DRIE) has become an enabling technology for the fabrication of many integrated microsystems, including accelerometers and gyroscopes, micro-fluidic devices, sensors, electrostatically actuated devices, and devices requiring back side optical access. The ability to etch deep Si structures with anisotropic sidewalls hundreds of microns deep has established a new set of devices in the MEMS area. Significant improvements in equipment and understanding of the process conditions have improved device yield and performance, and process reliability. Even with these improvements, several process issues are not well understood and often limit applications for the process. For example, sidewall morphology is often dominated by scalloping created by the iterative deposition-depassivation-etch cycle. Scalloping may make it difficult for deposition of materials on the sidewalls post DRIE or create non-optimal flow conditions for micro-fluidic devices. In addition, profile control of deep structures as a function of aspect ratio has not been optimized. For example, we have observed that creating positively tapered trench sidewalls often results in a trench bottom that exhibits a characteristic micromasked, grassy appearance. Conversely, eliminating the grass often results in a profile that undercuts the etch mask. Depending on the application, these phenomenon prevent the use of DRIE for device fabrication or cause the process to be optimized for specific structures thus preventing yield of other structures. In this presentation, we report on our efforts to vary DRIE process conditions to optimize sidewall profile and sidewall morphology as a function of aspect ratio. Structures considered in this study range from 10 microns to 700 microns in width, with etch depths to several hundred microns. We observe that passivation time, as well as ion energy, and ion flux in both the depassivation and etch cycles, have significant effect on the sidewall profile as a function of aspect ratio. We have also included morphing experiments in this study, where morphing is changing DRIE process parameters as a function of total process time. To optimize sidewall profile and morphology, the magnitude of the process changes during the morphing process is not necessarily linear with time. Results of these experiments will also be reported.

Sandia National Laboratories is a multi program laboratory operated by Sandia Corporation, a Lockheed Martin Company for the United States Department of Energy’s National Nuclear Security Administration under contract DE-AC04-94AL85000.

Vapor phase XeF₂ has been used in the fabrication of various types of devices including MEMS, resonators, RF switches, and micro-fluidics, and for wafer level packaging. In this presentation we demonstrate the use of XeF₂ Si etch in conjunction with deep reactive ion etch (DRIE) to release single crystal Si structures on Silicon On Insulator (SOI) wafers. XeF₂ vapor phase etching is conducive to the release of movable SOI structures due to the isotropy of the etch, the high etch selectivity to silicon dioxide (SiO₂) and fluorocarbon (FC) polymer etch masks, and the ability to undercut large structures at high rates. Also, since XeF₂ etching is a vapor phase process, stiction problems often associated with wet chemical release processes are avoided. Monolithic single crystal Si features were fabricated by etching continuous trenches in the device layer of an SOI wafer using a DRIE process optimized to stop on the buried SiO₂. The buried SiO₂ was then etched to handle Si using an anisotropic plasma etch process. The sidewalls of the device Si features were then protected with a conformal passivation layer of either FC polymer or SiO₂. FC polymer was deposited from C₄F₈ gas precursor in an inductively coupled plasma reactor, and SiO₂ was deposited by plasma enhanced chemical vapor deposition (PECVD). A relatively high ion energy, directional reactive ion etch (RIE) plasma was used to remove the passivation film on surfaces normal to the direction of the ions while leaving the sidewall passivation intact. After the bottom of the trench was cleared to the underlying Si handle wafer, XeF₂ was used to isotropically etch the handle Si, thus undercutting and releasing the features patterned in the device Si layer. The released device Si structures were not etched by the XeF₂ due to protection from the top SiO₂ mask, sidewall passivation, and the buried SiO₂ layer. Optimization of the XeF₂ process and the sidewall passivation layers will be discussed. The advantages of releasing SOI devices with XeF₂ include avoiding stiction, maintaining the integrity of the buried SiO₂, and simplifying the fabrication flow for thermally actuated devices. Sandia National Laboratories is a multi program laboratory operated by Sandia Corporation, a Lockheed Martin Company for the United States Department of Energy’s National Nuclear Security Administration under contract DE-AC04-94AL85000.

The STiGer cryoetching process can be alternatively used to the Bosch process or the cryogenic process to etch high aspect ratio structures. It has been developed thanks to our knowledge of the passivation mechanisms in cryoetching. In the standard cryogenic process, patterned Si substrates cooled down to very low temperatures are exposed to continuous SF₆/O₂ plasmas. A SiO_xF_y-type passivation layer is formed on the sidewalls and prevents etching. This film has the property to desorb under ion bombardment or when the substrate is heated. We also showed that SiF₄/O₂ plasmas can be used to create or reinforce a passivation layer in cryogenic etching.

The STiGer process consists of cycling passivation steps (SiF₄/O₂ plasmas) and etching steps to get vertical structures. The etching steps can be either isotropic (SF₆ plasmas) or anisotropic (SF₆/O₂ plasmas). Like the cryogenic process, it is required to cool the Si substrate with liquid nitrogen.

The STiGer process combines advantages of both Bosch process and cryogenic process. Due to the cyclic passivation steps, the SiO_xF_y film is stronger than in “standard” cryoetching. In addition, the passivation layer desorbs when the substrate is heated back to room temperature. Thus, unlike the Bosch process, there is no need to clean the microstructures and the chamber walls after each process run. Moreover, the robustness is enhanced in comparison with “standard” cryoetching : the profiles are less sensitive to temperature variations.

But, like the standard cryogenic process, a cooling is required and like in Bosch etching, a scalloping is present on the sidewalls. However, it is possible to minimize this effect by tuning the etching and the deposition steps.

We will present our most recent performances with the STiGer process. Our objectives are to etch sub-micron trenches and holes that will be further used for the realization of integrated capacitors and Through Silicon Vias (TSV). But obviously, the STiGer process can be utilized for silicon micromachining in general.

Finally, we will see how such a process can amplify Columnar MicroStructures (CMS).