AVS2010 Session PS-WeM: Plasma Surface Interactions (Fundamentals & Applications) I

Fabrication of latest DRAM capacitor structure requires precise etch profile control of silicon dioxide due to the continuous trend of narrowing pitch and high aspect ratio (HAR) features. While a number of issues are recognized such as twisting and bottom distortion, bowing became an outstanding subject for DRAM technology development for its complexity to cope with the bottom CD; even slight bowing leads to interference with the adjoining structures, and adjustment of process conditions frequently accompanies decreased bottom CD. In the present report we explore the effect of DC superimposition in capacitively-coupled plasma (CCP) as a countermeasure, taking advantage of its controllability on necking level at the mask facet.

Generally speaking, bowing is induced by the reflected ions at the mask facet attacking silicon dioxide sidewalls. Moreover, shrunk mask entrance interferes with incident radicals to transfer to the hole bottom, narrowing its size. One of the solutions utilizes high ion energy, but our results demonstrated a strong correlation between mask necking and bottom CD, thus the evaluation focused on optimization of mask necking.

Next, observation of deposition at the silicon dioxide sidewall varied with process parameters lead to systematic understandings of its physical amount and local enhancement, as well as the declining behavior at the removal process. By means of process parameters, the necking degree of the mask opening was controlled and the relationship among necking, bowing and bottom CD was examined.

As a result, it is necessary to improve necking at mask opening to minimize bowing and to keep bottom CD simultaneously. Optimization of process parameters enables etch profile enhancement by dispersing necking location, which normally decreases selectivity to mask. However, DC-superimposed CCP facilitated maintaining selectivity to mask with preferable etch profile, and less bowing with sufficient bottom CD.

We present work on the development of a cryogenic silicon etch process suitable for etching shallow and high aspect ratio nanoscale features below 50 nm for use in nanophotonics applications. With shrinking feature sizes, profile and critical dimension control tolerance is reduced and appropriate processes must be developed. Cryogenic silicon etching using SF₆-O₂ offers several advantages over fluorocarbon or heavier halogen based processes. For example, low bias voltages can be used, reducing mask erosion and ion damage. In addition, the etching process is not purely ion dependent which reduces some of the problems at small feature sizes associated with the ion angular distribution and ion interaction with the sidewall which can cause less than ideal profiles. Furthermore, sidewall contamination is minimal eliminating critical dimension (CD) variations due to etch residue cleaning. Two challenges to creating a suitable cryogenic SF₆-O₂ process for 50-100 nm features and below, is optimizing the passivant to eliminate undercut and reducing the etch rate enough to control the process. Furthermore, an etch process which changes in time accordingly to the etch depth and aspect ratio may be necessary for features below 20 nm.

The cryogenic SF₆-O₂ based silicon etching process was investigated in an Oxford Instruments ICP 380 using a L18 Taguchi design of experiments (DOE) matrix. For the DOE, trench type features sized 300-500 nm are investigated. Parameters varied include pressure, temperature, RF power, ICP power, He backing pressure, and oxygen content. The effects on the etch rate, selectivity, profile angle, and surface roughness were examined. The process was then finely tuned for etching of densely packed silicon trenches ranging from 100 to 10 nm. These features are patterned both with electron beam lithography and nano-imprint lithography techniques. Resist selectivity is high in both cases: from 10:1 to 20:1. Vertical and smooth sidewalls were obtained . Etched patterns were used to create nanophotonic devices such as nanospectrometers and laser waveguides and imprint masks for high resolution applications.

A complete understanding of the nature of fluorocarbon (FC) plasma systems necessarily includes a description of CF_x species behavior, including CF, CF₂, and CF₃. Our current research focuses primarily on understanding the gas-phase properties and reactions and gas-surface interactions of CF molecules produced from sparsely polymerizing CF₄ and C₂F₆ plasmas. An enriched understanding of these systems can elucidate the mechanisms contributing to film growth and may pave the way for enhanced plasma deposition and etching applications. To this end, we have employed laser induced fluorescence spectroscopy (LIF) and optical emission spectroscopy (OES) to probe the gas-phase behavior of CF, including calculations of rotational and vibrational temperatures. From these analyses, we determine that CF rotational states equilibrate with the plasma gas temperature at around 300 K. In addition, time-resolved actinometry has been employed to investigate gas-phase kinetics of the CF molecule as well as other CF_x species in a range of FC systems. We have also extended the LIF studies to our unique imaging of radicals interacting with surfaces (IRIS) technique which probes the gas-surface interface during plasma processing. CF species exhibit a surface gain in density, with surface scattering coefficients greater than unity for Si and ZrO₂ substrates, indicating production of the molecule at film-passivated surfaces. For comparison, IRIS results for CF₂ in the same plasmas will also be discussed. Surface analyses by high-resolution x-ray photoelectron spectroscopy (XPS) and variable angle spectroscopic ellipsometry along with the gas-phase data have culminated in a proposed mechanism for gas-surface interactions of these molecules during plasma processing of Si and ZrO₂ whereby the contributions of both CF and CF₂ molecules to film formation is summarily developed.

The energy of ions bombarding the substrate is critical in plasma etching (and deposition) of thin films. In conventional plasma processing, employing a sinusoidal substrate electrode voltage, the ion energy distribution (IED) is often very broad. However, as film dimensions approach the atomic level, control of the IED becomes critical. For example, selectivity considerations often dictate a narrow IED with a specified peak energy. In this work, semi-analytical models and particle-in-cell (PIC) simulations are employed to achieve “designer” IEDs, i.e., distributions with a desired shape and energy spread. This is accomplished by applying tailored voltage waveforms on the substrate electrode (spike, staircase, judiciously distorted square wave, etc.). Such waveforms can provide, for example, nearly mono-energetic IEDs or other desired shapes. Semi-analytic model results are compared with those of PIC simulation to identify the range of validity of the semi-analytic model. Predicted IEDs are also compared with experimental data under both collisional and collisionless sheath conditions. Strategies to control the energy flux of bombarding ions or to distribute the total energy flux to different energies will also be discussed.

Work supported by DoE Plasma Science Center and NSF.

With scaling of advanced electronic devices, plasma-induced damage (PID) has been investigated extensively from various viewpoints. Although suppressing PID is one of the critical issues in plasma process optimization, there have been few reports which correlate the plasma parameters to device performance in terms of PID.

This study discusses one of the PID mechanisms, physical damage induced by ion bombardment on Si surface. We propose a new comprehensive framework linking an ion energy and the distribution function to device parameters, i.e., a unified PID design.¹⁾ The framework is based on a modified range theory²⁾ and an analytical device-degradation model.^3),4) To verify the validity, we performed both experiments to clarify the damaged-layer structures (the thickness, defect site density, and the electrical properties) by novel techniques⁵⁾ and simulations (molecular dynamics and device simulations) to understand the quantitative effects.

We demonstrate prediction of performance degradation in metal-oxide-semiconductor field-effect transistors (MOSFETs) damaged by an inductively coupled plasma reactor which can apply the bias with two different frequencies (400 kHz and 13.56 MHz). The model prediction indicates that, in typical etching processes, the damaged-layer thickness can be determined primarily by an average self-dc-bias voltage rather than applied bias frequencies. This implication is found to be in good agreement with experimental results. Moreover, one can estimate also variation in device parameters from basic plasma parameters. Thus, it is concluded that the proposed framework is a key concept for future process and device designs.

1)K. Eriguchi et al., IEDM Tech. Dig. (2008) 443.

2)K. Eriguchi et al., to be published in Jpn. J. Appl. Phys., 2010.

3)K. Eriguchi et al., Proc. Symp. Dry Process (2009) 267.

4)K. Eriguchi et al., IEEE Electron Device Lett. 30, 1275 (2009).

5)K. Eriguchi et al., Jpn. J. Appl. Phys. 47 (2008) 2446.

A novel dual-source inductively coupled plasma (ICP) system was designed and built to control the electron energy distribution function (EEDF) in the plasma, and the ion energy distribution (IED) on the substrate. The main ICP source has a Faraday shield to minimize the RF component of the plasma potential. The substrate electrode, as well as a “boundary” electrode in contact with the plasma, can be independently biased by DC or RF voltages, of the desired waveform, to influence the IED. A secondary tandem ICP source can inject plasma, radicals or metastable atoms to the main ICP to influence the EEDF. The main ICP source was characterized using a Langmuir probe (LP), trace rare gas optical emission spectroscopy (TRG-OES), and an electrostatic ion energy analyzer. Emphasis was placed on pulsed plasma operation to achieve better control of the IED (as well as the ion angular distribution). With the Faraday shield installed, the plasma potential was several volts lower, and the peak-to-peak RF voltage of the plasma potential was suppressed to 1-2 V, as compared to the case without Faraday shield, allowing for smaller spread of the IED. The plasma potential, and thus the peak of the IED could be precisely controlled by the voltage applied to the boundary electrode. Accurate control of the ion energy and width of the IED is important for processes such as atomic layer etching, for which the threshold energies between etching and sputtering differ by only several volts. During the OFF period of a square wave modulation of the plasma power (50 μs ON, 50 μs OFF), the electron temperature decayed from 3.1 eV to less than 0.25 eV, with only a 20 % drop in plasma density for a 10 mtorr pressure, 200 W (average) power argon plasma. Time resolved EEDFs were also measured by the LP and compared to those extracted from TRG-OES experiments during the ON and first few ms of the OFF time. Tailored voltage waveforms were used to obtain “designer” ion energy distributions on the substrate. Finally, results for other gases (such as krypton and oxygen) will be discussed and compared to those obtained for argon plasmas.

Work supported by the DoE Plasma Science Center and NSF

Direct wafer bonding is a “simple” method of directly connecting wafers, with suitable (in terms of micro-roughness and flatness) surfaces, permanently to each other, by bringing them into contact and subsequently annealing them. The conventional process for hydrophilic oxidized Silicon surfaces (native as well as thermal oxide) is well understood, and explained the following way:

Up to 100°C the substrate surfaces are held together via van der Waals interaction which is mediated by a few monolayers of water. In the range of 100-200°C the water diffuses away from the interface both along the interface and through the oxide into the crystalline bulk, where it reacts with the silicon and forms oxide. The increase of the bond strength from 50% to 100% of Si bulk strength is usually attributed to a closing of gaps at the interface [1], which starts at the softening temperature of the thermal oxide at around 850-900°C.

Low temperature plasma activated direct wafer bonding for a pair of native oxide – thermal oxide interfaces is a process that lowers the required annealing temperatures necessary for reaching high bond strength. Bulk strength can be realized by plasma activation with subsequent annealing at 300°C. At this temperature conventional wafer bonding reaches half of Si bulk strength, and is limited by gaps at the bonding interface. The mechanism behind this improvement compared to the non activated process is still under discussion.

To clarify the mechanism for this commercially available process, different bonding experiments were performed to evaluate the lifetime of the surface activation and the achievable bond strength when using substrates with various orientations. Interfaces of bonded wafer pairs were investigated by transmission electron microscopy (TEM). TEM images clearly show that there is no discernible interface between the native oxide on one side and the thermal oxide on the other side.

By covering half of the wafer during plasma activation, comparisons between the activated and non-activated region could be made by atomic force microscopy, by spectroscopic ellipsometry, by Auger analysis and by X-ray photoelectron spectroscopy.

It was found that the top surface stoichiometry is chemically changed, which favors bonding. Finally a model for the mechanism that explains the experimental results will be presented.

[1] Q.-Y. Tong, U. Gösele, Semiconductor Wafer Bonding: Science and Technology, Wiley, (1998)