AVS1996 Session MS-ThA: Advanced Manufacturing Equipment and Processing - Cleaning Technology

Thursday, October 17, 1996 1:30 PM in Room 201A

Thursday Afternoon

Start	Invited?	Item
1:30 PM	Invited	MS-ThA-1 An Example of Technology Innovation Resulting in a Successful Product B. Mattson (Mattson Technology, Inc.) The semiconductor industry is driven by productivity increases. Most of the historical sources of productivity gains are now approaching diminishing returns. As a result, the semiconductor equipment industry's model of "technology at any cost" is no longer valid. The future requires technology and productivity combined, without compromise, achieve the lowest total overall cost. The combination is best achieved in the design phase. COO and OEE should be calculated early in the concept and feasibility stage, not just in the product introduction stage for use as a marketing tool. The Aspen product series is an example of this new product development paradigm. Several innovative technologies have been successfully implemented on a common platform. The method by which these innovations were achieved in a timely and cost-effective manner will be presented.
2:10 PM		MS-ThA-3 Temperature and Concentration Effects on Ozone Ashing of Photoresist W. Gardner, A. Baddorf (Oak Ridge National Laboratory); W. Holber (Applied Science and Technology, Inc.) Ozone is an established method for removing photoresist from semiconductor wafers that bypasses traditional wet-chemical processing, yet does not introduce oxide damage or mobile ion contamination which may occur with the use of plasma-based stripping tools. This study evaluates the effectiveness of unassisted ozone (i.e., without UV radiation) in photoresist removal using high concentrations, up to 10% by weight, of ultrapure ozone produced by an ASTeX Model AX8100 Ozone Generator.Photoresist removal was studied using single-crystal silicon samples mounted in a UHV compatible chamber. The photoresist was exposed to the ozone-oxygen mixture from the generator at atmospheric pressure and at 4 standard liters per minute. Resist thickness was measured using in situ laser interferometry. Resist removal was thermally activated with little removal at room temperature. Typical photoresist removal rates at a mole fraction ozone concentration of 0.06 ranged from 0.5-12 nm/s for substrate temperatures ranging from 100-300 degC, respectively. These rates compare favorably with those produced by other dry-process stripping tools. Removal rates follow standard Arrhenius behavior from which an activation energy of 5.2 KCal/mol was determined. This result is significantly lower than reported in the literature and may be more accurate since the substantial shrinkage of photoresist with temperature was accounted for in our results. Removal rate was also found to be a linear function of ozone concentration with a slope of 123 nm/s/unit mole fraction at a substrate temperature of 200 degC.ORNL is managed by Lockheed Martin Energy Research Corp. for the U.S. DOE under contract no. DE-AC05-96OR22464.
2:30 PM		MS-ThA-4 Defect Reduction and Cost Savings through Re-inventing RCA Cleans - A Joint Research and Manufacturing Project G. Ouimet, E. Fisch, G. Gale (IBM Microelectronics); D. Rath, S. Cohen (IBM T.J. Watson Research Center) RCA-type cleans, (also referred to as SC1, SC2 cleans) have been used in semiconductor manufacturing for decades. These chemical solutions, as developed by Kern and Puotinen in 1965(1), are multi- purpose treatments that, until recently, have been viewed as innocuous to silicon based surfaces, while providing moderate chemical cleaning of both organic and metallic residues. The concentrations and temper- atures employed have changed little over the last 30 years. Historically these mixtures of water, hydrochloric acid (for SC2) or ammonium hydroxide (for SC1) and hydrogen peroxide are mixed to a 5:1:1 volume ratio respectively, and used generally at temperatures at or above 60 degrees C. This is a comprehensive study using surface analysis techniques to test residue removal, silicon surface roughening, oxide etch rates, and standard particle cleaning efficiency due to the effects of SC1 and SC2 chemical concentration and temperature. For the SC1 bath, the effects of impinging high-frequency sonic energy on the wafer surface at different cassette slot pitches, as well as temperature and concen- tration variables, on cleaning efficiency is also investigated. The authors have found that low(er) concentration SC1 and SC2 baths (in concert with sonic energy (megasonics) for the SC1), lead to higher particle cleaning efficiencies, equivalent residue removal, reduced silicon roughening, and extended bath-life in a tank processor. These effects add up to reduced defect densities on semiconductor devices at a net lower cost. Chemical usage and disposal volumes are also reduced. Electrical test data on both DRAM and microprocessor devices are presented. Data from reducing concentrations on a spray-type chemical processor are also discussed.
2:50 PM		MS-ThA-5 Vapor Phase Cleaning of Sodium from Silicon Surfaces S. Beck, M. George, D. Bohling, K. Young, D. Moniot, B. Felker (Air Products & Chemicals, Inc.) Sodium is one of the most deleterious contaminants in microelectronics processing. This contaminant is typically removed from silicon surfaces by means of wet cleaning baths. The current move toward single wafer processing and cluster tools requires the development of vapor phase cleaning processes. In this work we report two vapor phase methodologies that are capable of removing sodium from silicon surfaces. The first method is a one step thermal process. Silicon wafers intentionally contaminated with less than a monolayer of NaOH are exposed to 1,1,1,5,5,5-hexafluoro-2,4-pentanedione (H\super +\hfac) at elevated temperatures. This process proceeds at temperatures up to 300\super o\C and total pressure up to 700 torr, and H\super +\hfac partial pressure up to 1 torr. The second method is a two step process. First the surface is exposed to a 4% hydrogen/ 96% nitrogen downstream microwave plasma and an anhydrous ammonia ambient. This converts the sodium to a more reactive state such as sodium amide. Next hexamethyldisilazane (HMDS) is reacted with the activated sodium species resulting in the formation of volatile sodium hexamethyldisilamide. This process occurs at temperatures below 225\super o\C and pressures below 1 Torr. For both methods, examination of the surfaces by x-ray photoelectron spectroscopy reveals that the sodium has been removed to below the detection limit of this analytical technique (< 0.2 atomic percent). The mechanisms related to sodium removal are discussed and the final state of the surfaces are described.
3:10 PM		MS-ThA-6 Post High Dose Implant and Post Via-Etch Photoresist Stripping and Cleaning without the Use of Acids and Solvents H. Xu, R. Bersin (ULVAC Technologies, Inc) It is desirable to eventually eliminate the use of acids and/or special solvents to clean wafers after dry photoresist stripping because of the high cost and environmental concern associated with chemicals. In order to do this, it is required that the dry photoresist stripping process does not generate water insoluble residues in the case of post high dose implant stripping or post etch stripping. Our approach to achieve the above goal is to strip the photoresist, which has been chemically altered and damaged during the ion implantation or reactive ion etching (RIE), in a layer by layer fashion according to the chemical composition of each layer, using either a microwave downstream plasma or a low damage RIE process. We have found that RIE with a low self bias voltage is very effective in removing the hard carbon-like skin layer which forms on the resist during high dose implantation. After this layer is removed, the remaining bulk resist can be ashed by the microwave downstream process and any ashing residue on the wafer surface can be washed off by deionized water, as witnessed by SEM observation. In addition, there is no charge damage to the gate oxide, no mobile ion and heavy metal contamination on the wafer surface due to the RIE process. This was monitored with CHARM II wafer, CV shift and VPD-AA surface analysis techniques, respectively. Examples of post via-etch ashing will also be presented in the meeting. Again, the RIE process is found useful in removing the etching plasma damaged resist skin layer and the polymer residue left on the via bottom. The significance of the RIE process directionality to the cleaning the bottom of ever smaller and deeper vias will be discussed.
3:30 PM		MS-ThA-7 In Situ Cleaning of LPCVD Tools using a Thermal NF\sub 3\ Etch Process A. Johnson, R. Pearce, C. Schneider (Air Products and Chemicals, Inc.); T. McGaughey, R. Gibson (Aspect Systems, Inc.); B. Metteer (Sematech, Inc.) In semiconductor manufacturing, low pressure chemical vapor deposition (LPCVD) is used for thin film deposition (e.g. Si\sub 3\N\sub 4\, polysilicon). LPCVD involves thermally decomposing (420 to 780 \super o\C) a source gas over the silicon substrate at low pressure. Material is deposited not only on the silicon wafer, but also on the walls of the quartz-vacuum chamber. After a cumulative deposition to a thickness of approximately 20 \mu\m on the chamber walls, this material needs removing to preempt particle shedding. Current practice for cleaning LPCVD Si\sub 3\N\sub 4\ tubes involves removing the quartz tube from the furnace and wet etching with HF, resulting in acid waste and 12 to 24 hours of equipment downtime. This paper describes an in situ clean process that has been integrated into semiconductor manufacturing operations. The thermal NF\sub 3\ process is a simple retrofit to existing LPCVD tools. The furnace is cooled to the cleaning temperature and isolated from the process pump, then filled with N\sub 2\, while pumping with a heated venturi. NF\sub 3\ gas flows until the Si\sub 3\N\sub 4\ has been cleaned from the quartzware. The clean process was monitored using a quadrupole mass spectrometer (QMS) designed for fast sampling of a subambient atmosphere. The stoichiometry of the overall reaction that removes the Si\sub 3\N\sub 4\ film is: Si\sub 3\N\sub 4\ + 4NF\sub 3\ = 3SiF\sub 4\ + 4N\sub 2\ The time evolution of the NF\sub 3\ and SiF\sub 4\ concentration measured by QMS was used to determine when the clean was complete. At end point, the NF\sub 3\ partial pressure increases, while there is a corresponding decrease in that for SiF\sub 4\. A Si\sub 3\N\sub 4\ (5 \mu\m) deposit can be cleaned in 50 min. The paper will describe how the clean was optimized and how the LPCVD process was successfully requalified for both metal and particle contamination following the thermal NF\sub 3\ clean.
3:50 PM		MS-ThA-8 Effects of Plasma Etching Damage and Cleaning Treatment on Titanium Silicide Formation T. Nakahata, M. Tuda, K. Ono (Mitsubishi Electric Corporation, Japan) Plasma damage on Si surfaces caused during SiO\sub 2\ etching processes is increasingly a serious problem because of its significant influences on contact resistivity. Cleaning processes to remove such damaged layers are thus essential to achieve low contact resistivities. This paper presents effects of plasma etching damage and after cleaning treatment on Ti silicide formation, by comparing surfaces with and without chemical dry etching (CDE) processes after oxide etching. Experiments were performed with p-type Si(100) wafers covered with a layer of SiO\sub 2\. After etching the oxides in ECR C\sub 4\F\sub 8\/O\sub 2\ plasmas, the Si surfaces were cleaned through O\sub 2\ plasma exposure and dipping in H\sub 2\SO\sub 4\/H\sub 2\O\sub 2\. Subsequently, CDE was done using CF\sub 4\/O\sub 2\ plasma afterglows, followed by conventional RCA treatment and dipping in HF solution. On Si surfaces thus cleaned, thin Ti films were sputter deposited and then annealed to enhance silicidation. The XPS spectra of Si surfaces after dipping in HF solution showed that there were SiC and SiO\sub x\ on CDE-untreated samples, while they were completely removed on CDE-treated ones. The SIMS profiles after Ti deposition and anneling clarified that Ti and Si diffused mutually on CDE-treated samples, while the Ti-rich layer and Si substrate were separated by highly concentrated oxygen layer on CDE-untreated ones. These results indicate that without CDE, the damaged layer inhibited the Ti silicidation, probably because Ti reacted with residual SiO\sub x\ to form titanium oxides at the interface, and thus a partial Ti layer saturated with oxygen prevented diffusion of Si into Ti.
4:10 PM		MS-ThA-9 Integrated Dry Cleaning of Contamination Resulting from Reactive Ion Etching of Silicon Dioxide A. Lawing, A. Muscat, H. Sawin (Massachusetts Institute of Technology); T. Fayfield (FSI International) Reactive Ion Etching (RIE) etching of SiO\sub 2\ in fluorocarbon gas mixtures is widely used in the semiconductor industry for the patterning of contacts and vias. We have developed a dry cleaning sequence that removes both the polymer and oxide residue resulting from an oxide etch and ashing process. This dry cleaning sequence utilizes UV/Cl\sub 2\ to remove polymer contamination and vapor phase HF/IPA to remove oxide contamination. The cleaning chambers and an analytical chamber with X-ray Photoelectron Spectroscopy (XPS) capability are connected under vacuum via a system of transfer rods. Multiple processes, as well as the associated XPS analysis, can be performed in this apparatus without exposing the sample to ambient contamination. In this manner we can effectively mimic a clustered cleaning process. After etching in a CF\sub 4\/CHF\sub 3\ plasma, the silicon surface is covered with a residue layer consisting of ~40 \Ao\ of polymer contamination and an underlying oxide layer of thickness on the order of a native oxide (~15 \Ao\). A 30 minute O\sub 2\ ash thins the fluorocarbon layer, while thickening the underlying oxide. An initial UV/Cl\sub 2\ process removes the surface polymer, but some carbon remains and cannot be removed by UV/Cl\sub 2\ at this stage. This carbon is presumably incorporated in the underlying oxide, or is present at the oxide/silicon interface. An HF/IPA process removes the oxide layer, but the level of carbon contamination is apparently increased, due to the exposure of the incorporated carbon discussed earlier. A second UV/Cl\sub 2\ process removes this residual carbonaceous material.
4:30 PM		MS-ThA-10 Carbon Contamination in an Etching Reactor using Electron Cyclotron Resonance Plasma and the Effect of N\sub 2\ Addition K. Miwa (Fujitsu VLSI Ltd., Japan); H. Kojiri (Fujitsu Ltd., Japan); M. Aoyama (Fujitsu VLSI Ltd., Japan); K. Nagase (Fujitsu Ltd., Japan); K. Higuchi, M. Inoue (Fujitsu VLSI Ltd., Japan) We observed the decline of etching rate of TiN film after etching of wafers coated with photoresist and we could prevent the decline by addition of N2 gas into the etching gas, in a single wafer reactor using Electron Cyclotron Resonance (ECR) plasma of BCL3 and CL2 mixed gas for etching process in semiconductor manufacturing. Carbon was detected on the TiN surface etched in the reactor with the plasma after photoresist etching by X-ray Photoelectron Spectroscopy (XPS). That TiN surface was contaminated by carbon in the reactor during the etching process. N2 gas was added to reduce carbon contamination. After photoresist etching with N2 added etching plasma, etching rate of the TiN did not decline and also carbon was not detected on the wafer surface etched in the reactor. Therefore we concluded that carbon contamination on the TiN surface derived from photoresist caused the decline of etching rate. The effect of N2 addition must be attributed to the reaction between nitrogen radical in the N2 added etching plasma and carbon in the reactor.