Potentials for heterogenous integration of Ga₂O₃ with high thermal conductivity materials such as diamond for enabling energy-efficient kV-class power devices are being discussed. The integration alleviates Ga₂O₃ material drawbacks such as its low thermal conductivity and inefficient hole conductivity. The benefits of heterogeneous integration are for example demonstrated through electrical and thermal simulations of a Ga₂O₃-Al₂O₃-diamond superjunction based Schottky barrier diode. The simulation studies show that the novel device has potential to break the R_ON-breakdown voltage limit of Ga₂O₃, while showing relatively low rise in temperature compared to conventional devices. As step into their realization, experimental Al₂O₃ assessment namely ledge features in the capacitance-voltage (CV) profiles of Ga₂O₃ metal-oxide-semiconductor (MOS) capacitors were investigated using UV-assisted CV measurements; an interface trapping model is presented whereby the capacitance ledge is associated with carrier trapping in deep-level states at the Al₂O₃/Ga₂O₃ interface. Trench-Schottky Barrier diodes with breakdown voltage in excess of 1.5kV were demonstrated. First steps for the materials integration of Ga₂O₃ with diamond towards a superjunction based trench-Schottky barrier diode, including epitaxial growth of Ga₂O₃ on single crystal diamond substrates are being reported.

This letter reports the high performance β-Ga2O3 thin channel MOSFET with T gate and degenerately doped source/drain contacts regrown by Metal Organic Chemical Vapour Deposition (MOCVD). Device epitaxial layer was grown by Ozone MBE. Highly scaled T-gate (LG=160-200 nm) was fabricated to achieve enhanced RF performance and passivated with 200 nm Silicon Nitride (Si3N4). Peak drain current ( ID,MAX) of 285 mA/mm and peak trans-conductance (gm) of 52 mS/mm were measured at 10 V drain bias with 23.5 Ω mm on resistance (Ron). Metal/n+ contact resistance of 0.078 Ω mm was extracted from Transfer Length Measurements (TLM). Channel sheet resistance was measured to be 14.2 Kiloohm/square from cross bar structure. Based on TLM and cross bar measurements, we determined that on resistance (Ron) is possibly dominated by interface resistance between channel and regrown layer. Different growth methods originating from MBE channel layer and MOCVD regrown n++ layer can cause this high interface resistance. A gate-to-drain breakdown voltage(V_DG) of 192 V is measured for L_GD= 355 nm resulting in average breakdown field (E_AVG) of 5.4 MV/cm. This E_AVGis the highest reported among all sub-micron gate length lateral FETs. And highest overall without using any intentional field plate techniques. Current gain cut off frequency (f_T) of 11 GHz and record power gain cut off frequency (f_MAX) of approximately 48 GHz were extracted from small signal measurements. f_T is possibly limited by DC-RF dispersion due to interface traps which need further investigation. We observed moderate DC-RF dispersion at 200 ns pulse width (for both output and transfer curve) which can corroborate our theory. We recorded f_T.V_BR product of 2.112 THz.V for 192 V breakdown voltage which is similar to GaN HEMT devices. Our device surpasses the switching figure of merit of Silicon because of low on resistance and high breakdown voltage, and competitive with mature wide-band gap devices. Proper surface cleaning between channel and regrowth layer and sub-100 nm T gate device structure can pave the way for better RF performance.

Beta Gallium Oxide (Ga₂O₃) is well positioned excel in high power density applications due to its wide band gap, critical field strength, multiple shallow donor species, and melt grown native substrates. Monolithic integrated circuits (ICs) can advance Ga₂O₃ by reducing the size, weight, and connectivity parasitics of components. Lateral topologies with thin epitaxy on insulating substrates enable simple fabrication and integration of RF components. This work utilizes this system to demonstrate a fundamental circuit, the diode full-wave rectifier, with an accompanying design study of the interdigitated lateral diode topology.

The devices (Fig. 1) are fabricated from a 65 nm Si-doped Ga₂O₃ epitaxial layer grown by MBE on a Fe-doped Ga₂O₃ substrate. Epitaxy carrier concentration is measured to be 2×10¹⁸ cm^-3 from C-V test structures (Fig. 2). The cathode is a Ti/Al/Ni/Au Ohmic contact annealed at 470 ^oC. The devices are isolated with a BCl₃ ICP mesa etch. A field-plate and surface passivation oxide of 80 nm thick Al₂O₃ is deposited by ALD. The anode is a Ni/Au Schottky contact. A full-wave rectifier and 16 diode variations are evaluated. The diodes have square and rounded contacts; anode finger counts of 1, 2, 4, and 8; and anode-cathode lengths (L_A-C) of 5, 7, and 12 µm. Anode length is 4 µm and width is 48 µm. The diodes in the rectifier have round contacts, 4 anode fingers, and 12 µm L_A-C (Fig. 3). The rectifier is measured on-chip with micro probes. An AC signal is generated with a high-voltage amplifier and measured on an oscilloscope. The output of the rectifier to a 47 kΩ load is measured differentially, using a voltage divider to protect the oscilloscope from voltage spikes (Fig. 4).

The rectifier successfully demonstrates full-wave rectification of sine waves up to 144 V_rms (205 V peak) and 400 Hz (Fig. 5). The rectifier demonstrates 83 % efficiency and 0.78 W peak power. To the authors’ knowledge, this is the first demonstration of a diode full-waver rectifier IC in Ga₂O₃. From the lateral diode design study, rounded contacts improve the average breakdown voltage (V_bk) by 20% (+41 V) without effecting specific on-resistance (R­_on,sp) (Fig. 6). The number of anode fingers does not statistically affect V_bk, and improves average R­_on,sp by 18% (-0.45 mΩ-cm²) at eight (Fig. 7). Scaling L_A-C to 5, 7, and 12 µm also scales average R_on,sp to 2.0, 2.9, and 8.6 mΩ-cm². Average V_bk scales as well, but with no change between 5 and 7 µm L_A-C (248, 242, and 341 V) (Fig. 8). The J-V characteristics of a single diode (round contacts, eight fingers, 5 µm L_A-C) are included in Fig. 9.

Beta gallium oxide (β-Ga₂O₃) has shown promise for high-voltage power devices and power switching due to its large critical field strength E_c estimated at 8 MV/cm [1]. Dielectric passivation and testing under Fluorinert immersion [2] are used to increase breakdown voltage V_bk and avoid air breakdown, respectively, with the highest V_bk lateral Ga₂O₃ devices using polymer passivation [3]. The polymer benzocyclobutene (BCB) exhibits high dielectric strength, low parasitics, and good manufacturability [4,5]. It may be loaded with hexagonal boron nitride (hBN), improving thermal conductivity, dielectric response, and mechanical durability [6]. Coatings can be applied via aerosol jet printing, allowing multiple experimental conditions across devices on a single sample. Here, lateral β-Ga₂O₃ MOSFETs encapsulated with hBN-loaded BCB (hBN-BCB) which exhibit significantly enhanced V_bk compared to devices encapsulated with BCB alone or without encapsulation.

Si-doped β-Ga₂O₃ was grown epitaxially on a semi-insulating, Fe-doped (010) Ga₂O₃ substrate via molecular beam epitaxy to a nominal thickness of 65 nm and a doping of 2.8+-0.2x10¹⁷ cm^-3. Ti/Al/Ni/Au ohmic contacts were deposited and annealed at 470 °C for 60 s in N₂. Ni/Au gates were deposited on a gate oxide of 20 nm Al₂O₃^, followed by a passivation oxide of 85 nm Al₂O₃. Thick Au contacts were formed using evaporation and electroplating. Devices with BCB or hBN-BCB were encapsulated using an Optomec AJ200 aerosol jet printer. Inks consisted of Cyclotene 4022-35, cyclohexanone and terpineol, with or without hBN.

V_bk was tested under air or Fluorinert (Figure 2). Devices tested under Fluorinert, BCB, and BCB plus Fluorinert showed a 1.7x improvement in V_bk over air. Devices with hBN-BCB showed an improvement of 3.7x over air and 1.35x over BCB alone. The hBN-BCB-coated devices (N=6) show significant improvement in V_bk over the devices coated BCB alone (N=3) with p<0.011 (single-tail heteroscedastic T-Test).

Device performance of the highest-V_bk device are shown in Figure 3. The device, before encapsulation, had R_on of 683 Ω∙mm, I_max of 3.42 mA/mm, G_m,peak of 1.14 mS/mm, V_th of -3.8 V, V_off of -6.5 V, and V_bk of 951 V (E_crit,avg 1.23 MV/cm). Device performance was unaffected by hBN-BCB encapsulation (Fig. 3b) excepting a change in V_off to -8 V. No significant gate leakage was observed during device operation or breakdown. Breakdown likely occurred due to peak fields exceeding the E_crit of one or more materials at the drain-side edge of the gate. These results provide a significant improvement over existing encapsulation approaches in β-Ga₂O₃ lateral MOSFETs.

We report on the growth, fabrication, and wafer-scale characterization of lateral high-voltage MOSFETs with ~120-160 mA/mm on current on a large area 1” Synoptics™ insulating substrate. A ~170nm Si-doped β-Ga₂O₃ channel with an electron concentration of ~3 x 10¹⁷ cm^-3 was grown via metalorganic chemical vapor deposition (MOCVD) on a 1” Fe-doped (010) bulk substrate which was subjected to a 30min HF treatment prior to growth. The growth was done using Agnitron Technology’s Agilis 700 MOVPE reactor with TEGa, O₂, and Disilane (Si₂H₆) as precursors with Ar as the carrier gas. A ~210nm unintentionally doped (UID) buffer layer was grown on top of the substrate. The source and drain ohmic contacts were selectively regrown and patterned with a BCl₃ Reactive Ion Etch (RIE) and HCl wet clean. n⁺ β-Ga₂O₃ was then grown via MOCVD using Silane (SiH₄) as the silicon precursor and a Ti/Au/Ni Ohmic metal stack was deposited on the regrown regions. A 30nm Al₂O₃ gate dielectric was deposited via ALD at 300C. Lastly, a Ni/Au/Ni gate metal was deposited. The channel sheet charge was measured to be uniform across the wafer (4.6 x 10¹² cm^-2 ± 0.6 x 10¹² cm^-2), estimated from the MOSCAP C-V characterization (V_GS of +10V (accumulation) to pinch-off). The output and transfer characteristics were measured across the wafer for devices with 1/1.5/1 μm L_GS/L_G/L_GD dimensions. The pinch-off voltage had a large variation across the wafer (-30 ± 15V). The apparent charge profile from the C-V curves indicates the presence of a parasitic channel at the substrate-epilayer interface which is distributed non-uniformly across the wafer. The on-current (I_D) measured across the wafer was more uniform about 140 ± 20 mA/mm (V_GS = +10 V, V_DS = 15 V). CV measurements and transfer characteristics indicate a significant density of slow traps (negatively charged) at the dielectric/semiconductor interface, leading to a repeatable shift in the transfer curve from the 2^nd scan onward. The MOSFET devices were measured without any field plating or passivation in Fluorinert and the three-terminal destructive breakdown voltages for 5μm and 20μm L_GD were 0.65 and 2.1 kV, respectively. Demonstration of wafer-scale growth, processing, and characterization of MOSFETs on a domestic bulk substrate platform reported here is a key step highlighting the technological potential of beta-Gallium Oxide. Acknowledgments: We acknowledge funding from II-VI Foundation, UES Inc. and discussions with AFRL.

Off-state leakage currents in lateral β-Ga­₂O₃ FET devices have previously been attributed to the presence of unintentional Si (n-type) at the interface between epitaxial layer and the substrate^[1-5], i.e. a parallel leakage conducting channel. Fe-doping (>10¹⁹cm^-3) near the surface of the β-Ga­₂O₃ substrate, followed by thermal annealing, has been proven to compensate the unintentional Si impurities, to some degree, thereby reducing leakage current in devices; however, elevated off-state currents and low on-off ratios are still observed in these devices^[5]. This work is to provide an analytical model to describe the observed device frequency dispersion due to parallel conductive Si-accumulation layers. Particularly, the dispersion is not associated with active traps as generally believed^[6-8].

Lateral β-Ga­₂O₃ transistors here were processed on a MBE-grown epitaxial layer on Fe-surface-implanted semi-insulating β-Ga­₂O₃ substrates, followed by thermal annealing^[5](Fig.1). The transfer characteristics of the device (Fig.2) reveals a large off-state leakage drain current (10^-6A/mm) and a small gate leakage current (10^-12A/mm). The gate-source capacitance-voltage (C_GS) and equivalent conductance-voltage (G_GS) profiles between 1kHz and 1MHz (Fig.3) reveal a background dispersion with frequency that is nearly independent of applied gate bias.

An equivalent circuit model is built for explaining impedance dispersion (Fig.4). The parallel leakage path along the entire UID/substrate interface due to Si contaminants provides a coupling path between channels and the probe pads, which are included in the analysis of the device. Therefore, the total capacitance (C_GS) will be the “ideal” capacitance (C_ideal) superimposed by the contributions from the capacitance and resistance underneath the gate pad(C_GP, R₁, C₁), the resistance of the parallel leakage path (R_s), and the capacitance and resistance under the channel (R₂, C₂). Utilizing this model, the measured C_GS and G_Gs are well fitted (Fig.5). The exclusion of traps in the model indicates parallel coupling, instead of traps, should predominantly account for observed frequency dispersion. Moreover, from the extracted R_s in Table.1, the Si concentration at epi/substrate interface is estimated around 1×10¹⁸cm^-3, which agrees with that measured from SIMS (Fig.1). This work provides an understanding of the electrical impact of the parallel leakage path of β-Ga₂O₃ devices at moderate frequencies. The signal generated by the parallel leakage can mislead impedance measurements, affecting further analysis such as D_it extraction in β-Ga₂O₃ MOSFETs.