AVS 72 Session AM2+EM+TF-FrM: Devices II

Fully-Depleted Silicon On Insulator (FDSOI) planar technology - an alternative to FinFET (3D field effect transistors) - address technologies involving very high energy efficiency, ultralow power consumption and cost reduction. 10 nm FD-SOI transistor requires complex metal on insulator (MOS) gate stacks. The MOS structure is composed of doped titanium nitride layers as metal gates, and SiON/HfON as gate-dielectric[1]. SiON is also called gate interlayer (IL). Thinning TiN layers results in better MOS performances. This is due to a known phenomenon called IL scavenging, where TiN acts as an oxygen reducer of the IL, which in turn reduces the IL thickness[2]. The targeted TiN thickness in the 10 nm-node FDSOI is closed to 2 nm, and the required equivalent oxide thickness (the electrical thickness of the IL/HfON insulator stack) is below 0,8 nm. As the layers thicknesses reach the nm-scale, it introduces new challenges regarding the electrical behavior of the MOSFET due to the heterogeneity of the materials in the gate stacks.

To address those challenges, the developments of an ultra-thin 2 nm metallic gate stack with sub-stoichiometric titanium nitride (TiN_x<1) are required. CEA-Leti has acquired a PVD deposition tool by co-sputtering to deposit complex metallic layers on 300 mm silicon wafers with an atomic-scale thickness control.

This study examines TiN_x ultra-thin films with thicknesses below 5 nm. TiN_x structural, optical and electrical properties are evaluated by X-Ray Reflectivity (XRR), stress measurements, sheet resistance measurements, spectroscopic ellipsometry, X-Ray Photoelectron Spectroscopy (XPS) and X-Ray Diffraction (XRD). TiN_x layer composition is investigated by Elastic Recoil Detection Analysis (ERDA) and X-Ray Fluorescence (XRF) analysis. Those layers have been integrated on simplified electrical devices to evaluate their impact on transistor key performance parameters (EOT, Vt, Jg, …).

This work was carried out in the framework of the FAMES Pilot Line of the Chips JU and the Platform for Nanocharacterisation (PFNC) funded by Horizon Europe grant 101182279, ANR NextGen project ANR-22-NEXTG-001, ANR programs “Recherche Technologique de Base” and "France 2030 - ANR-22-PEEL-0014".

Additional authors:

J.Kanyandekwe, J.Lespiaux, P.Faucherand, L.Brévard, A. Magalhaes-Lucas, A. Souhaité,

CEA-Leti, France

References:

[1] C. Fenouillet-Beranger, et al, “Pursuing the FD-SOI roadmap down to 10 nm and 7 nm nodes for high energy efficient, low power and RF/mmWave applications,” Solid-State Electron. 231, 109264 (2026).

[2] T. Ando et al., Ultimate Scaling of High-κ Gate Dielectrics: Higher-κ or Interfacial Layer Scavenging, Materials 2012, 5, 478-500

Ambipolar organic field-effect transistors have seen years of development and have been a topic of interest now for several decades. The dual-polarity allows for more simple circuit architecture for organic electronics. Generally, the performance of planar ambipolar organic transistors is poor and requires the deposition of two different organic semiconductors [1-3]. Frequently, the mobility is well below 1 cm² V^-1s^-1, usually by orders of magnitude. Here, we look at bio-organic polypeptides to reduce the fabrication steps for flexible electronics. We show that polypeptide-based materials have potential in organic electronic devices, more specifically, they are seen to make excellent organic ambipolar transistors. In this study, organic field-effect ambipolar transistors (OFETs) were fabricated using poly-D-lysine, poly-L-ornithine and poly-L-aspartic acid combined with poly(3,4-ethylenedioxythiophene):polystyrene sulfonate (PEDOT:PSS). Under ambient light, the poly-D-ornithine based devices showed higher overall on-state currents, while the poly-L-lysine-based devices exhibited significantly higher on-state currents under dark conditions, with differences of at least two orders of magnitude. Thus, we have two distinct types of bio-organic ambipolar transistor devices. Both the poly-D-lysine and poly-L-ornithine devices also demonstrated relatively long carrier lifetimes, ranging from 10^-6 to 10^-3 s, while the bio-organic ambipolar transistor made from poly-L-aspartic acid combined with PEDOT:PSS has a mobility of 1 cm² V^-1 s^-1. Comparing the calculated and experimentally measured band-gap energies provides complementary information about the electronic structure of the polypeptide materials. Overall, these results demonstrate and highlight the potential of these polypeptide materials for organic electronic applications and highlight the potential of polypeptides as tunable materials for low-voltage bio-organic ambipolar transistors.

1. Baeg, K.-J. et al., IEEE Electron Device Lett. 34, 126–128 (2013).

2. Zhang, Z. et al., Adv. Funct. Mater. 25, 6112–6121 (2015).

3. Kraft, U. et al.,. Adv. Mater. 27, 207–214 (2015)

Next-generation power conversion systems increasingly rely on SiC power MOSFETs to minimize switching losses and maximize power density. Conventional SiO₂ gate dielectrics limits maximizing the gate capacitance and drive current, making higher-k dielectrics attractive to improve switching characteristics.However, to date, severe defect densities at the direct high-k/SiC interface has prevented strict high-k adoption.Consequently, recent work has focused on utilizing a dielectric bilayer with SiO₂ serving as the interface dielectric with SiC to enable low defect densities and a high-k stacked on top in an attempt to gain the “best of both worlds”.Despite some reported successes, there remain critical gaps discussing what fundamental advantages or limitations exist from this dielectric bilayer approach.

In this presentation, we present analysis of the available design space for layered dielectrics in SiC-based MOSFETs.Our analysis operates under three fundamental assumptions related to applied gate bias, avoidance of time-dependent-dielectric-breakdown (TDDB), and the requirement to be high-k (effective dielectric permittivity greater than the permittivity of the semiconductor).We show that when these assumptions are applied then the available design space for layered dielectrics is quite limited and calls into question advantages of a layered approach.

Sandia National Laboratories is a multi-mission laboratory managed and operated by National Technology & Engineering Solutions of Sandia, LLC (NTESS), a wholly owned subsidiary of Honeywell International Inc., for the U.S. Department of Energy’s National Nuclear Security Administration (DOE/NNSA) under contract DE-NA0003525.

SAND2026-21413A