AVS 70 Session EM-ThP: Electronic Materials and Photonics Poster Session

In the era of the Fourth Industrial Revolution, the utilization of high-performance and high-speed DRAM is increasingly expanding. In response to this trend, the integration density of DRAM is also improving. Since transitioning to the 10 nm design rule, scaling is continuously demanded not only for the DRAM cell size but also for the wiring. The wiring, responsible for supplying electrical signals and power to the DRAM, consists of 4 to 5 layers, with the final wiring utilizing Al lines. Low resistance is necessary to accommodate the delivery of high power for the Al layers.

The composition of Al wiring is as follows: Ti is applied as a barrier metal to connect with the Via tungsten, followed by the formation of Al wiring with a thickness of over 500 nm using the PVD method. On top of this, TiN is applied as an anti-reflecting layer. The Al wiring is patterned using lithography and dry etching techniques. With the scaling of Al wiring, the spacing between metal lines has decreased to 50 nm or less. This means that the space for dry etching the 500 nm-thick Al has become 50 nm, resulting in an aspect ratio of 10:1, posing extreme difficulty. This has led to various serious defects, with the most common being Al undercut defects.

The defect occurs when etching extends from the bottom of the Al layer to the sidewalls, causing it to disconnect. The cause of this issue is that as the aspect ratio increases, the polymer, which serves to protect the Al sidewalls during dry etching, cannot effectively reach the bottommost part, resulting in etching. To overcome this, if the shape of the Al line is formed with a positive slope, it becomes highly susceptible to Al bridge defects.

Two methods were devised to overcome this, implemented in Samsung's 20 nm DRAM technology to confirm their effectiveness. Firstly, it was observed that Al undercut defects primarily concentrated at the edges of wafer. This is influenced by the temperature of the high chuck during dry etching, and it was found that precise temperature control was difficult with the current structure. Therefore, the chuck structure was modified from 2 zones to 4 zones to enable fine temperature adjustment, and the edge area was dry etched at a lower temperature to facilitate the transmission of more polymer.Secondly, the layout structure of the Al layer was reinforced. It was found that having discontinuous vulnerable patterns was more advantageous than continuously existing patterns. Therefore, irregular step patterns were created compared to patterns resembling hammers, and their effectiveness was confirmed.These two improvements were validated through test results of real 8G DDR4 products.

In this work, we combine simulations at force field (FF) up to hybrid density functional theory (DFT) level. Employing the MG2 force field [2], a comprehensive statistical ensemble of structural models for a-Si₃N₄ was generated through the melt-quench procedure, ensuring robust statistical significance in our analysis [3]. Adding charges to those models, we perform structural optimization using the HSE06 hybrid DFT-functional to ensure the localization of the band edges and defect trapping energies are well described. We identify a hitherto unknown mode of intrinsic polaronic trapping of electrons in a-Si₃N₄: Charging can generate either a K-center or Si-Si-type defect. At the same time, discharging recovers the amorphous network's original structure [3]. Crucially, this study bridges the previously fragmented understanding of charge trapping and hydrogen incorporation. We demonstrate that hydrogen plays a dual role: It can repair coordination defects, healing the network, yet also promotes Si-N bond breaking in strained areas, thus compromising the network integrity [4]. Our findings offer a unified perspective on the interplay between defect formation, hydrogen behavior, and charge trapping, providing insights critical for optimizing a-Si₃N₄'s electronic properties in nanoelectronic applications.

[1] Warren, W. L. et al.J. Appl. Phys.1993,74, 4034–4046.
[2] Marian, C. M.; Gastreich, M.; Gale, J. D.Phys. Rev. B2000,62, 3117–3124.
[3] Hückmann, L.; Cottom, J.; Meyer, J.Adv. Phys. Res.2024,3, 2300109.
[4] Cottom, J.; Hückmann, L.; Olsson, E.; Meyer, J.J. Phys. Chem. Lett.2024,15, 840–848,Selected for cover.

Cadmium Telluride (CdTe) thin-film solar cells have made significant progress in efficiency, with laboratory-scale tests surpassing 22.1%, edging closer to the theoretical Shockley-Queisser limit of around 32%. Recent research has been focused to integrate selenium (Se) into CdTe absorbers, creating band grading without CdS window layers. CdSe_xTe_1-x is a prominent candidate to enhance the short-circuit-current (Jsc) by bandgap lowering below 1.45 eV. While CdS window layer intermixing mitigates the lattice mismatch, it concurrently limits absorbing light in the critical 300 - 525 nm range, resulting in efficiency loss. Thus, strategies to overcome this drawback have been focused on introducing Se to create band grading. CdSe_xTe_1-x is promising, with bandgap lowering below 1.45 eV, pushing Jsc to their theoretical limit.

In this contribution, CdSe_xTe_1-x/CdTe devices were fabricated by vapor transport technology, and the mechanism of efficiency improvement was studied through in-situ Cu dopant profiling during light soaking. Moreover, devices were stressed at elevated temperatures simultaneously under various bias conditions, both with illumination and in the dark. The morphological and cross-sectional structure of the graded absorber were confirmed by Scanning Electron Microscopy and Electron Dispersive Spectroscopy. During light soaking, different intensities of light and temperatures were tested to characterize devices. Concurrently, we modeled the electronic structure of characterized devices using our in-house MATLAB modeling suites, connected to the external TCAD simulators, to explain the result with material and device input parameters. The results indicate that CdSe_xTe_1-x/CdTe devices have shallow donor and acceptor energy states near the main front junction interface. The concentration of Cu dopant is approximately 4 x 10¹⁴ cm³ in the wake-up condition. The Cu dopant progresses toward the front CdSe_xTe_1-x /CdTe junction during in-situ measurements.Interestingly, the stability of CdSe_xTe_1-x solar cells was found to be bias-dependent and device-specific during light and dark soaking. CdSe_xTe_1-x /CdTe devices without Cu dopant demonstrated depletion reduction width under light and dark-biased conditions. The depletion width of CdSe_xTe_1-x devices without Cu is reduced to approximately 47 % under applied soaking conditions. Simultaneously, efficiency, Voc, and FF decreased, whereas Jsc show no clear dependency. Under light soaking conditions at 95 C, the increases in Voc, FF, and efficiency depend on light soaking conditions. The peak efficiency after 9 hr light soaking at 95 C is 12.90 %.

We conducted a thorough analysis of vertical geometry NiO/Ga₂O₃ rectifiers using the Silvaco TCAD simulator to establish optimized breakdown voltages ranging from 1 to 7 kV. By manipulating key NiO parameters such as doping concentration (ranging from 10¹⁷ to 10¹⁹ cm^-3), thickness (ranging from 10 to 70 nm), and junction extension beyond the anode to form a guard ring (ranging from 0 to 30 µm), we determined the electric field distribution within each design. The factors of doping concentration, thickness, and junction extension were found to significantly influence the site of device breakdown, which could occur anywhere from the edge of the NiO extension to the edge of the top contact, consistent with experimental results. Further investigations also revealed varying breakdown voltages based on theoretical critical electric fields for different NiO bilayer thicknesses and doping concentrations.

Spin-On Hardmask (SOH) materials are pivotal in semiconductor manufacturing for their superior masking quality, alignment accuracy, process control, and cost-effectiveness, crucial in patterning formation. However, insufficient chemical bonding between SOH and other layers, improper spin speed, or thickness can lead to void formation. In 10nm-scale DRAM products, where pattern sizes are extremely small, SOH voids can cause defects such as bridging and discontinuity in cell transistor gates. This paper demonstrates methods to minimize SOH void formation during the manufacturing process, focusing on the bake time. During SOH baking, condensation reactions and thermal degradation occur, leading to outgassing. In the early stages of baking, polymer condensation is prominent, and once cross-linking is complete, outgassing due to condensation diminishes. However, as bake time increases, outgassing due to thermal degradation becomes more significant. Thus, minimizing void formation by reducing outgassing at the completion of condensation reactions can be observed, leading to improvements in defects such as bridging and discontinuity caused by SOH voids in final patterns.

Fundamentally, the back-end interconnect system is made up of two material types: a metallic conductor, and an insulating dielectric. With the ongoing push for high-performance computing, the higher device and power density as well as speed requirements for integrated circuits place new and more challenging demands on these materials. As the semiconductor industry perseveres toward a replacement for the copper conductor, multiple different challenges face dielectrics, including more stringent deposition control, patterning flexibility, and property specifications (electrical, mechanical, thermal, etc). Boron-based solids have been considered as an alternative to silicon-based dielectrics due to their combination of potentially ultra-low dielectric constant with robust mechanical, electrical, and chemical properties. This contribution will cover recent advances and future potential for boron-based dielectrics from our group and others.