AVS2010 Session GR+EM+MS+TF+MI-WeM: Graphene and Carbon-based Devices

The realization of a graphene-based electronic technology necessitates large-area graphene production, as well as the ability to integrate graphene with highly insulating films that act as the gate dielectric in field effect transistors (FETs). Graphene’s two dimensional nature allows for phenomenal electronic properties and ultimate scalability, but also makes it susceptible to doping and scattering by charged impurities, dangling bonds, and other defects that may derive directly from choice in gate dielectric and deposition technique. The nature and extent of the effect of the dielectric over-layer on conduction within the graphene channel is of fundamental interest in designing and producing graphene based FETs. Atomic layer deposition (ALD) has proven to be an excellent technique toward the integration of dielectrics with graphene and provides a means to produce high quality films for gate dielectrics at temperatures below 300C, but requires the use of a thin nucleation layer to promote complete coverage and to protect the graphene.

We present results on graphene FETs utilizing various gate dielectrics and various nucleation layers. Graphene was grown epitaxially on 100 mm SiC wafers and processed using standard photolithographic techniques. Al₂O₃ and HfO₂ gate dielectrics were investigated using SiO₂, TiO₂, and Al₂O₃ nucleation layers in various combinations. We show that choice of gate dielectric and nucleation layer can have a dramatic effect on transistor performance and charge carrier mobility. Saturation current, transconductance, and device hysteresis were examined in the fabricated FETs while charge carrier mobility and charge carrier density within the epitaxial graphene were evaluated using Van der Pauw structures. Graphene FETs utilizing Al₂O₃ and SiO₂ seeded dielectrics exhibit the best performance while TiO₂ seeded and unseeded devices exhibit large gate leakage currents resulting in non-functioning FETs. Additionally we provide evidence that the choice of dielectric and seed can significantly impact the Dirac point (minimum conduction), amount of hysteresis, and on/off ratio of the graphene FETs. Trends in saturation current, and transconductance appear be independent of nucleation layer and gate dielectric choice, indicating that conduction through the channel may be limited by mechanisms independent of the nucleation layer and gate dielectric.

In addition to the aforementioned performance metrics, FET performance after continued application of high electric fields across the channel will be reported. Finally, we examine how choice of channel length and width, along with transistor design, effect performance.

In this paper, we present our recent advancements in electrostatically transferring epitaxial graphene (EG) from SiC(0001) and SiC(000-1) to arbitrary glass substrates (including Pyrex). We will compare the electronic properties of electrostatically transferred EG and nominally-equivalent as-grown EG on SiC. These properties are measured using magnetoresistive, four-probe, and field effect transistor geometries. We feel this is a potential enabling technology for integration of graphene with structured and electronically-active substrates, such as MEMS and CMOS.

CVD-grown graphene on Cu has attracted wide interest since it can be readily transferred to arbitrary substrates. However, CVD-grown graphene has been shown to have lower mobilities and smaller domain sizes than EG. EG is difficult to transfer to arbitrary substrates. Currently two techniques exist to transfer EG – a gold/polymer film handle and thermal tape exfoliation [1,2]. While transfer is possible with these techniques, problems exist including contamination and damage, as measured by Raman spectroscopy.

To overcome the issues with the above mentioned transfer techniques, we have developed a technique capable of electrostatically transferring both patterned and chip-scale regions of EG to arbitrary glass substrates. We start with high-quality graphene (mobility 14,000 cm²/Vs and domains >100 um²) grown using an Ar-mediated approach [3,4]. In electrostatic graphene transfer, a large electric field is applied between the donor graphene sample (anode) and the acceptor insulating substrate (cathode). This strong electrostatic force deposits graphene on the insulating surface. Electrostatic transfer of EG is a clean technique which, unlike other EG transfer methods, does not contaminate the graphene with adhesive residue or gold contaminates. Both few-layer graphene from SiC(000-1) and monolayer graphene from SiC(0001) have been transferred using this technique.

Our initial attempts at EG transfer have been extensively characterized with Raman spectroscopy and atomic force microscopy. Raman spectroscopy shows that the inherent strain in EG has been partially relaxed. Furthermore, a defect peak (D peak) is frequently not seen in the transferred graphene indicating that the procedure does not significantly damage the graphene film.

Sandia is a multiprogram laboratory operated by Sandia Corporation, a Lockheed Martin Company, for the United States Department of Energy under contract DE-AC04-94AL85000.

[1] D. Lee et al. Nano Lett. 8, 4320 (2008)

[2] S. Unarunotai et al. APL 95, 202101 (2009)

[3] W. Pan et al. submitted to APL (2010)

[4] K. Emtsev et al. Nature Mat. 8, 203 (2009)

We present a study of ozone-based atomic layer deposition (ALD) of Al₂O₃ films on graphene and bulk graphite. Uniform deposition of scalable device-quality high-k dielectrics on graphene is a substantial hurdle for the implementation of conventional FET devices as well as novel device structures exploiting the unique transport properties of graphene. Trimethylaluminum (TMA) / O₃ processes are found to result in uniform Al₂O₃ depositions on graphite and graphene surfaces (1), in contrast to common TMA / H₂O-based processes which result in nonuniform nucleation at defects and step edges.

In order to further examine the nature of interactions between TMA / O₃ and graphene, we utilize in-situ x-ray photoelectron spectroscopy (XPS) coupled via a UHV transfer line to an ALD reactor. Morphology of deposited films is also examined ex-situ using atomic force microscopy (AFM). We examine the impact of several parameters on Al₂O₃ deposition. Choice of deposition temperature is critical, as etching of graphene by O₃ is observed at elevated temperatures (2) but dielectric quality is degraded at low temperature (3). We also examine the impact of surface condition on Al₂O₃ composition particularly with regard to partially reacted TMA precursor molecules; various surface treatments are employed to approximate realistic device processing conditions. Finally, the effect of variations in purge time between ALD precursor pulses is studied; a reduction in deposition with increased purge time indicates that weakly bonded precursor molecules (TMA and O₃) are easily desorbed from the graphene surface.

This work is supported by the NRI SWAN and MIND centers.

1: B. Lee, et. al., Appl. Phys. Lett. 92 (20), 203102 (2008)

2: G. Lee, et. al., J. Phys. Chem. C 113 (32), 14225 (2009)

3: S. K. Kim, et. al., J. Electrochem. Soc. 153 (5), F69 (2006)