AVS1996 Session MS-TuA: Advanced Manufacturing Equipment and Processing

Tuesday, October 15, 1996 2:00 PM in Room 201A

Tuesday Afternoon

Start	Invited?	Item
2:00 PM	Invited	MS-TuA-1 Selection Criteria for Advanced Semiconductor Manufacturing Equipment M. Liehr (IBM T.J. Watson Research Center) Like the automotive and the steel industry, the semiconductor industry is very capital intensive with costs for new factories now in the range of $1-2B. The fraction of the total build cost of new semiconductor factories taken up by processing equipment has risen steadily over the past two decades. By now, and more so in the near future when we transition to 12" wafers, equipment constitutes the vast majority of the total factory cost. It is therefore imperative for semiconductor manufacturers to properly address and manage the equipment selection process to assure adequate return on assets through high equipment utilization. This presentation will discuss the driving forces behind the equipment cost trends, and will address the most significant issues in equipment selection and as well as equipment deployment philosophy.
2:40 PM		MS-TuA-3 Characterisations of Silicon Dioxide Contact Holes Processes Developed in a Commercial High Density Plasma Source P. Berruyer (CEA-LETI, France); R. Blanc (SGS-Thomson); O. Joubert, P. Czuprynski, F. Bell (France Telecom-CNET) High-aspect ratio sub-half-micron contacts were etched in SiO2 using a high-density C2F6 plasma generated by a commercial inductively coupled, low pressure reactor. Process development studies have shown that high aspect ratio contact holes can be open in thick dielectric layers with a good selectivity to the underlying silicon. Minimization of RIE Lag is obtained by using high bias power conditions, which on the other hand induce a degradation of the photoresist, described as a graphitisation of the resist. The degradation induces an important roughness at the edges of the resist structures which lead to the creation of striations in the silicon dioxide as the pattern transfer in the SiO2 proceeds. The deformation of contact holes can be minimized by using different plasma operating conditions. XPS studies have allowed a complete chemical topography analysis of high aspect ratio SiO2 contact holes. Using appropriate flood gun conditions, a complete separation of the XPS peaks originating from the resist mask and from the fluorocarbon polymer deposited on the bottom of contact holes is possible. The XPS analyses show, in particular, that the fluorination of the polymer on the bottom of contact holes strongly increases with the aspect ratio of the contact hole and that the fluorination of polymers deposited on the contact hole sidewalls is even more important. The performance of the source are also evaluated through yield measurements on 10K 0.3um contact chains and contact resistance on TiSi2
3:00 PM		MS-TuA-4 Wire Resistance Measurements for Evaluating Advanced High Density Metal Etchers H. Kawamoto, K. Tokashiki, H. Miyamoto (NEC Corporation, Japan); N. Ciampa, A. Kornblit, J. Lee (Bell Laboratories) With the metal interconnect geometries required for future high-speed logic devices, variations in wire resistance due to variations in etched profiles becomes an important issue. A wire resistance measurement is proposed to evaluate the global and local profile variations of two advanced commercial reactors, a helicon and a transformer coupled plasma. The wire lengths are 100 microns and the wire width and distance to the nearest neighbor are systematically varied. The wire resistance is correlated to cross-sectional Scanning Electron Micrographs (SEMs). We observed a close relationship between plasma uniformity and wire resistance uniformity, which implies that a very uniform plasma was effective for reducing profile variations across the wafer. Even though these global variations were small, the actual profiles still must be determined by SEM since the resistance technique cannot distinguish between tapered or undercut profiles with the same cross-sectional area. However, there is no need to take SEMs of both the center and edge of the wafer. With increasing spacing between adjacent wires, the resistance decreased because the etching profile had become tapered and the effective cross-sectional area had increased. This trend was observed for both etchers. Additionally, local resistance variations were higher when the linewidths were narrower because the absolute amount of variation was a larger percentage of the total cross-sectional area. Thus, we find that the wire resistance technique is a useful complementary diagnostic that offers a rapid means for evaluating etching tools for global and local profile variations.
3:20 PM		MS-TuA-5 Comparison of an Electrostatic Clamp to a Mechanical Clamp in Polysilicon Etching J. Meyer, K. Olson, L. Jerde (Tegal Corporation) A Johnsen - Rahbek type electrostatic clamp (ESC) is compared to a mechanical clamp (MC) used as a wafer stage in a low pressure, high density plasma reactor. The clamps were tested in production tools used for etching polycrystaline silicon and tungsten silicide on 150 and 200 mm wafers. Process transfer from the MC to the ESC will be discussed. The etch rate was found to be slightly lower using the ESC when compared to the MC at identical powers and pressures, however the optimum etch rate uniformity improved from 8.3% (max - min , 6 mm edge exclusion) to 3.2% (max - min, 3 mm edge exclusion). The etch rates for the ESC can be made identical to the MC by adjusting the operating parameters. Process data sampled from a 10,000 wafer marathon using the ESC will be compared to data from the MC including critical dimension control for multilevel stack etching. Long term reliability of the ESC will also be discussed.
3:40 PM	Invited	MS-TuA-6 Development and Evolution of a New Multi-Zone RTP Cluster Tool Technology M. Moslehi, Y. Lee (CVC Products); C. Schaper (Stanford University); P. Spence (Sandia National Laboratories) Rapid Thermal Processing (RTP) technology is a single-wafer alternative to batch furnace equipment for thermal anneal, oxidation, and chemical-vapor deposition fabrication processes. While there has been a significant amount of interest in RTP for selected wafer processing applications, production acceptance of RTP has been relatively slow and limited primarily to the atmosphric silicide formation processes. Although RTP technologies provide a useful capability for rapid temperature cycling and short-time low-thermal-budget processing, widespread qualification of RTP for mainstream silicon chip production has been hindered due to temperature measurement and control problems. The conventional RTP temperature sensors suffer from various sources of error such as wafer emissivity variations and lamp light interference effects. Moreover, the device patterns and conventional scalar temperature control methods can produce both large-scale and localized wafer temperature non-uniformities, resulting in slip dislocations and process non-uniformity problems. The transition to larger wafer diemeters (existing 200-mm and emerging 300-mm wafers) has driven accelerated development of the enabling precision process control capabilities and improved equipment architectures for insertion of RTP in state-of-the-art semiconductor technology nodes. We will present a historical overview of the significant developments in the area of RTP manufacturing equipment technologies over the past 10 years. These enabling developments include: (i) multi-zone RTP equipment designs; (ii) multi-point temperature probes with real-time compensation for wafer emissivity and lamp light interference effects; (iii) improved equipment architecture to eliminate the wafer pattern effects on temperature uniformity; (iv) cluster tool implementation of RTP equipment for integrated processing applications; (v) development of model-based virtual RTP reactors for equipment design optimization, reactor scaling, and development of multi-variable dynamic temperature control strategies; (vi) modular RTP equipment architecture based on the Universal Process Module approach for wider process windows as well as capability for extended applications in the areas of rapid thermal anneal, oxidation, nitridation, and chemical-vapor deposition processes. This presentation will also present a case study on model-based development of a commercial multi-zone RTP cluster tool product based on the pioneering R&D work at Texas Instruments on development and implementation of the multi-zone RTP technology for agile semiconductor IC manufacturing. These enabling developments have removed the major roadblocks for successful insertion of multi-zone RTP equipment technologies in state-of-the-art production fabs. We will also discuss the RTP requirements and trends for the emerging 300-mm wafer processing applications.
4:20 PM		MS-TuA-8 Reactor Studies for Highly Ionized Sputtering M. Grapperhaus, M. Kushner (University of Illinois, Urbana-Champaign); Z. Krivokapic (AMD) Highly ionized sputtering is offering a promise for filling high aspect ratio vias and trenches for deep submicron technologies. Rossnagel and Hopwood presented experimental data from an ICP sputtering system. In our work, we present results from studying various kinds of reactor designs, potentially suitable for ionized sputtering by using an equipment and plasma simulator, HPEM. In the model we take into account magnetron sputtering, power deposition, transport, and plasma chemistry. Our studies are done for copper deposition, mainly because of better available electron impact ionization cross section data. In the paper we present the simulator and various test studies, looking at magnetron power, ICP power, location and number of coils, position of wafers, pressure, and different inert gases. In most promising cases, ion and neutral fluxes are then used in a profile simulator to study feasibility of filling dual damascene structures.
4:40 PM		MS-TuA-9 Characterization of Fluorinated TEOS Oxide Films Deposited in a Low Pressure PECVD Reactor M. Weise, S. Selbrede, L. Arias, D. Carl (Mattson Technology, Inc.) Fluorinated silicon dioxide films were deposited in a commercial PECVD reactor using TEOS, Oxygen, and C\sub 2\F\sub 6\. The depositions were carried out using dual RF frequency power at low pressure, 500-750 mTorr. Film properties were investigated as a function of RF power, pressure, gas flows, and wafer temperature. Fluorine content, dielectric constant, refractive index, stress, deposition rate, and uniformity are among the film properties studied. Special attention was paid to the stability of these properties in air, in boiling water, and after subsequent annealing. The baseline TEOS process is unusual in that high compressive stress values can be achieved, up to about 300 MPa. It was thought that this high initial stress would lead to improved stability at higher fluorine concentration. Film stress was found to be quite compressive, even at high fluorine concentrations. Good film stability was observed for fluorine concentrations up to 10 % (peak ratio; Si-F/Si-O). Fluorine concentration was determined by FTIR and correlated with SIMS. Refractive indices as low as 1.40 and dielectric constants as low as 3.4 were measured. This work demonstrates that a stable, production-quality, fluorinated oxide film can be deposited in this reactor.