PCSI2027 Session PCSI1-WeA2: Thermal Transport, Surface Processing & Nanofabrication

Two-dimensional (2D) materials such as graphene and transition metal dichalcogenides (TMDs) offer transformative potential for scaled nanoelectronics, but severe thermal dissipation bottlenecks arise at van der Waals (vdW) interfaces with dielectric substrates. Gate-induced electrostatic pressure (P_elec) provides a promising contact-free mechanism to actively modulate thermal boundary conductance (TBC) across these interfaces without inducing mechanical damage [1]. In this study, we present a comprehensive multiscale numerical framework coupling Density Functional Perturbation Theory (DFPT) calculations with phonon transport modeling to elucidate the physical mechanisms governing pressure-enhanced TBC across 2D-substrate interfaces.

Interfacial vdW interactions between 2D sheets and amorphous SiO₂ substrates were calculated from first principles using Density Functional Theory (DFT) implemented in VASP, then parameterized using a modified Buckingham potential fitted to DFT energy-distance curves, yielding precise vdW spring coupling constants K_s(h). Our model incorporates localized surface roughness statistics (RMS height Δ_rms, auto-correlation length L_cor, and average surface slope of the roughness Δ_rms/L_cor), energy minimization, and full flexural phonon density of states. On flat substrates, TBC enhancement (dG/dP) is driven exclusively by vdW bond compression, yielding pressure sensitivities of dG/dP = 0.016 ms^-1K^-1 for unencapsulated graphene/SiO₂ and 0.025 ms^-1K^-1 when encapsulated, eliminating internal flexural phonon bottlenecks.

When realistic substrate roughness is introduced, partial delamination occurs at zero external pressure, suppressing initial conductance G₀. Applied electrostatic fields draw suspended regions toward the substrate, expanding the real contact area ΔA/ΔP and simultaneously stiffening interfacial vdW bonds ΔK_s/ΔP at contact peaks. Consequently, dG/dP exhibits a non-monotonic dependence on surface slope, peaking sharply at Δ_rms/L_cor ≈ 0.1, where contact area expansion and bond compression each contribute ~50% to overall TBC enhancement. Beyond this threshold, severe delamination reduces G₀, suppressing pressure sensitivity. Furthermore, stronger interfacial adhesion increases G₀ and consequently dG/dP, whereas stiffer 2D materials (higher bending stiffness D_bend) resist conforming to rough surfaces, creating air gaps that lower TBC. Gate-induced carrier densities up to 2×10¹³ cm^-2 enhance flexural (ZA) phonon repopulation via electron-phonon coupling (Γ_el-ph), adding ~4% to total TBC [5]. These findings establish key predictive guidelines for active thermal management in 2D electronics.

Heterostructures of two-dimensional (2D) vdW materials have emerged as a platform for novel nano- and opto-electronic applications because they offer numerous stacking combinations that may lead to properties not achievable in individual layers. However, the thermal properties of these heterostructures have received less attention, even though they are essential, as Joule heating can generate hotspots in such devices. In 2D transistor applications, hexagonal boron nitride (hBN) is typically used as an interlayer between the 2D channel and the substrate to enhance electron mobility [1] and contribute to heat spreading. Heat transfer between 2D materials and their substrates is driven by a combination of the overlap of the vibrational density of states (vDOS) of the flexural phonons in the 2D layer and the substrate [2,3,4] and vdW coupling strength at the interface. When a 2D layer is coupled to a substrate, the interfacial restoring force opens a gap in the vDOS, with the gap frequency determined by the interfacial force constant and the layer’s mass density [5], and when multiple layers are added to the structure, the phonon branches become hybridized [6], creating new features in the vDOS. Whether one can control the vDOS of the heterostructure by selecting the composition and the stacking order in the vdWH to enhance heat transfer to the substrate remains an open question.

In this work, we compute phonon dispersions from density functional theory for the constituent monolayers and construct a coupled dynamical matrix for the out-of-plane flexural phonon branches. We also compute the van der Waals spring constants for the interlayer and substrate interactions. We then calculate the layer-projected vDOS to determine how modes originating in the transport layer contribute to motion in the substrate-interface layer and obtain the thermal boundary conductance (TBC) into the substrate. We observe that coupling to the substrate through long-wavelength breathing modes that displace all layers of the vdW heterostructure dictate the TBC.

[1] H. Y. Lan, R. Tripathi, J. Appenzeller, and Z. Chen, IEEE Electron Device Lett. 45, 1337 (2024). [2] J. H. Seol, I. Jo, A. L. Moore, L. Lindsay, Z. H. Aitken, M. T. Pettes, X. Li, Z. Yao, R. Huang, D. Broido, N. Mingo, R. S. Ruoff, and L. Shi, Science 328, 213 (2010). [3] C. J. Foss and Z. Aksamija, 2D Mater. 6, 025019 (2019). [4] G. C. Correa, C. J. Foss, and Z. Aksamija, Nanotechnology 28, 135402 (2017). [5] B. Amorim and F. Guinea, Phys. Rev. B 88, 115418 (2013). [6] Z.-Y. Ong, Phys. Rev. B 95, 155309 (2017).

Selective removal of sacrificial SiGe is a key step in forming suspended Si nanosheet channels in gate-all-around FETs (GAAFETs). As devices scale down, isotropic chemical dry etching (CDE) is increasingly adopted for channel release, while wet chemistries suffer from stiction and pattern collapse in narrow gaps. The exposed Si becomes the channel and the gate-dielectric interface, so release-induced damage maps directly onto the interfacial defect density (Dit) and subthreshold swing. Here we compare dry- and wet-released surfaces and provide a recovery solution based on sacrificial thermal oxidation.

Two candidates can degrade the interface: atomic-scale roughness and residual fluorine. CDE (a bias-free CF4/O2/N2 plasma) attacks the exposed Si once the SiGe is cleared, whereas wet release (peracetic acid with buffered oxide etchant) proceeds through oxidation of Ge-containing bonds and fluoride-assisted dissolution. AFM quantifies the morphological imprint: Rq reaches 1.79 nm after 30 s of CDE (16 times the wet value) and keeps increasing during over-etch, whereas wet-released Si stays near 0.1 nm even after 210 s. XPS isolates the chemical imprint: only dry-released Si shows an F 1s peak at 686.6 eV (SiOxFy), while Ge is below detection and the Si 2p oxide component stays at the native level on all samples.

A single sacrificial cure (5 min dry O2 oxidation at 800 °C growing 2.5 nm, followed by oxide strip) recovers both axes at once: Rq of the CDE surface drops by 59% to 0.74 nm, the wet surface stays pristine, and the fluorine disappears below detection on every sample. PEALD SiO2 cycle splits show identical growth on both surfaces (1.67 Å/cycle), so the electrical comparison probes the interface alone.

Because the cure erases the chemical difference, MOSCAPs (PEALD SiO2/HfO2/TiN) on four splits (dry/wet release × with/without cure) isolate the effect of the remaining roughness on Dit. For the uncured dry split we anticipate a mid-gap Dit on the order of 10^12 cm^-2 eV^-1, versus the low-10^11 range for the cured and wet-released splits. Measured Dit, VFB, and hysteresis will be presented, with correlation to GAAFET devices in fabrication.

A superconducting transmon qubit consists of a shunt capacitor in parallel with a nonlinear inductor, a Josephson Junction (JJ). The conventional JJ is composed of two superconducting aluminum contacts separated by thin amorphous aluminum oxide (AlO_x). It is believed that the high density of two-level system defects in or near the barrier limits the qubit performance. One promising route towards low-loss JJs is utilizing single-crystalline dielectric materials, which lack the structural disorder believed to be responsible for TLS in amorphous oxides. High-resistivity undoped float-zone Si is one of the lowest-loss dielectric materials at cryogenic temperatures and microwave frequencies. Based on first-principles calculations of Schottky barrier heights indicate that to achieve sufficient Josephson critical current density requires a Si barrier thickness in the 5~10 nm regime for Al contacts.

This work presents a fabrication process to realizesub-10 nm thick, high-aspect-ratio single-crystalline Si fins. Fins are defined on float-zone Si (110) by electron-beam lithography and anisotropic KOH etching through an LPCVD SiNₓ hard mask, which also serves as the shadow mask for the subsequent superconductor angle deposition. Following the anisotropic wet etching, a digital etching process based on repeated oxidation and hydrofluoric acid etching of the resulting oxide was developed until the desired thickness is achieved. Fin thickness as thin as 6 nm has been achieved. We have investigated oxidation methods ranging from room-temperature ozone oxidation to rapid thermal annealing (RTA) oxidation at various temperatures and ambients, with liquid and vapor HF for oxide removal, using cross-sectional transmission electron microscopy to determine the thickness and roughness of the barriers. RTA oxidation provides better oxide thickness tunability, and the ramp ambient governs the thickness uniformity along the fin. In this presentation, we will discuss how the choice of oxidation and etching method affects the fin thickness and the uniformity of the barrier.

Surface Acoustic Wave (SAW) devices are a foundation for telecommunications and sensor technologies. However, commercial deployment is bottlenecked by expensive cleanroom manufacturing, requiring vacuum-based physical vapor deposition and multi-step photolithography to pattern Interdigitated Transducers (IDTs) directly onto the piezoelectric film. While solution based Chemical Bath Deposition (CBD) offers a low-cost, benchtop alternative, undoped zinc oxide (ZnO) films exhibit high n-type conductivity due to unintentional incorporation of shallow-donor impurities, primarily hydrogen. This causes the applied RF signal to dissipate as a parasitic electrical short. To overcome these limitations, we introduce a dual-strategy approach. First, copper (5 at.% Cu) is introduced into the CBD precursor solution to act as a deep acceptor, trapping the free electrons and restoring the films piezoelectric properties. Second, films are grown onto glass pre-coated with a conductive Indium Tin Oxide (ITO) underlayer to terminate electric field lines and prevent energy dispersion into the substrate. Traditional lithographic IDTs are replaced with off-the-shelf Flexible Printed Circuit Boards and are mechanically coupled to the films. Electrical and acoustic characterization validates the success of this platform. Undoped CBD films show a flat and featureless response, whereas the 5 at.% Cu-doped films exhibit a well-defined Rayleigh resonance mode at 15.4MHz. The ZnO/ITO/Glass architecture demonstrated a significantly deeper reflection magnitude and an improved electromechanical coupling coefficient compared to films grown on bare glass. 3D Laser Doppler Vibrometry (LDV) confirms the out-of-plane Rayleigh wave generation, showing a 27% increase in peak mechanical displacement (56 pm vs. 44 pm) for the ITO-supported configuration. By combining wet-chemical defect engineering, structural field confinement, and mechanical off-the-shelf components, this work establishes a fully functional, highly accessible method for rapid, low-cost SAW device manufacturing.