ICMCTF2004 Session H3-1: Thin Films for Next Generation Devices
Time Period ThM Sessions | Abstract Timeline | Topic H Sessions | Time Periods | Topics | ICMCTF2004 Schedule
Start | Invited? | Item |
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8:30 AM | Invited |
H3-1-1 Ferroelectric Thin Films on Silicon Carbide for Next Generation Nonvolatile Memory and Sensor Devices
Mikael Östling (KTH, Royal Institute of Technology, Sweden) As a semiconductor material, silicon carbide (SiC) offers great advantages to overcome the physical device limitations in Si devices set by its materials properties. For example, Si devices are generally used below its maximum junction temperature of ~200°C and confined to blocking voltages of a few kilo-Volts. Due to its large band gap, SiC possesses a very high breakdown field and low intrinsic carrier concentration, which accordingly makes high voltage and high temperature operation possible. SiC is also suitable for high frequency device applications, because of the high saturation drift velocity and low permittivity. So far, dielectrics including AlN and TiO2 have been investigated on SiC, which shows that the best performance was obtained when those deposited insulators are integrated with SiO2. In ferroelectrics, the spontaneous polarization can be switched by an externally applied electric field, and thus are attractive for nonvolatile memory and sensor applications. In this work, a brief introduction to the materials and process technology of SiC including metal contacts to SiC, will be given. Particularly, the fundamental physics research and technology development for the successful realization of SiC diodes and transistors including BJTs and JFETs, will be described. The motivation for SiC Ferroelectric-FET will be then provided as well as the first experimental results from the prototype devices, which operated up to 300°C with memory function retained up to 200°C. |
9:10 AM |
H3-1-3 A Modeling of the Optical Properties of Thin ZnO-ZnMgO Films in a Double Barrier-quantum Well Structure
G. Krokidis, J.P. Xanthakis (NTUA, Greece); A.A. Iliadis (University of Maryland) Recently the optical activity in the UV range and the resonant tunneling (RT) behaviour of ZnO based quantum wells has been demonstrated [1]. The wells were 6nm and 8nm with emission at 345.55 nm and 348.22 nm respectively after excitation by a N2 laser and I-V characteristics showed 2 negative differential resistance peaks. Here we investigate the correlation between the optical and transport properties of this system by evaluating the localization of the energy levels in the quantum well. The wavefunctions of the levels spread out not only in the ZnMgO barrier material but also in the outer ZnO material and therefore a textbook model will not be sufficient. This system is large for ab-initio methods, hence we use an effective mass approach. The study shows that there are 3 distinct levels in the 6 nm well at 24.8, 97.6, and 211.0meV. The 2 peaks in the I-V can be explained by observing that the 211meV level is two orders of magnitude less localized than the other two levels. Similarly the levels in valence band are derived at 4.1, 16.0, and 32.6meV, and the allowed optical transitions are identified. Since the system is excited by a N2 laser, the de-excitation from the 211 level to the 32.6 below Ev level (only ?n=0 transitions are allowed) gives 3.54eV in close agreement with the experimentally observed 3.58eV. The level above Ec that gives the optical activity is "absent" in the transport data due to its poor localization, which can be explained if one examines the spread of the wavefunction in the entire system. Furthermore, we observed that although the degree of localization has been significantly reduced by decreasing the barrier width (as expected), the positioning of the levels in the wells remains almost unaffected. Hence by changing the barrier width b one can change the transport properties of the system without affecting optical properties which depend almost entirely on well width a. [1] A. Iliadis et al SPIE Vol.4650, pp67-74, 2002. |
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9:30 AM |
H3-1-4 High Density Ge Quantum Dots Prepared by High-vacuum Ion-beam Sputtering
H.H. Wu, J.M. Ting (National Cheng Kung University, Taiwan, R.O.C.) Numerous efforts have been made for the research and development of quantum dots due to its technological importance. The fabrication of quantum dots is almost exclusively accomplished by molecular-beam expitaxy (MBE) technique. Recently an e-beam evaporation process was also attempted. In this study, we have used a high-vacuum ion-beam sputter deposition technique to fabricate high-density Ge quantum dots (GeQD) on (100) silicon substrate. The new approach eliminates the need for expensive MBE equipment. The relationship between the growth parameters and the characteristics of GeQD was addressed. The growth parameters include substrate temperature, ion beam intensity, ion beam energy, growth pressure, substrate surface condition, and the use of an assisted ion source. The substrate temperatures used were 500 ~700. The ion beam intensity was varied through adjusting the inlet gas flow rate. The ion beam energy was controlled by ECR voltage to have 3 different energy levels. A total of 3 growth pressures were used. The substrate surface condition was modified by cleaning and oxide pyrolysis. For selected growth, an assisted ion source was used. The as-grown samples were characterized using atomic force microscopy (AFM) for surface morphology, high resolution transmission electron microscopy (HRTEM) and micro-Raman spectroscopy for microstructure, and photo luminescence (PL) for quantum confinement effect. |
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9:50 AM |
H3-1-5 New Metal Layers for Integrated Circuit Manufacture: Experimental and Modeling Studies
N. Iwamoto, N. Truong, E. Lee (Honeywell Electronic Materials) Copper migration continues to be an important consideration in new and emerging interconnect technologies. As line dimensions shrink and new low k materials are introduced into the IC structure, the danger of electrical failure due to copper migration increases. The search for better barriers and new copper alloys that resist migration are being sought. Important considerations are not only copper migration, but adhesion characteristics which add to the electrical failure phenomenon and also help determine the survivability of the metallic layers in the IC build up process. To understand the survivability issues, we have employed a combination of experimental and modeling studies to determine how the combination of metallic layers may interact. Both the experimental tests and the modeling have been found to be consistent and simple molecular models can be used to predict gross failure trends. These studies have directed us toward newer barrier and copper alloys layers that should be useful in the next generation. |
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10:10 AM |
H3-1-6 Characterization of Hot Wall Epitaxy Grown AgGaTe2 Films on KCI Substrate
R. Kumar (D.A.V. College, India); R.K. Bedi (Guru Nanak Dev University, India) Silver gallium telluride (AgGaTe2) films were prepared from the prereacted polycrystalline material by hot wall technique in vacuum of 1.3 X 10-3 Pa onto the KCl substrates kept at different temperatures (483-563 K). The experimental conditions were optimized to obtain better crystallinity of the films. The effect of substrate temperature on the structural, electrical and optical properties of the films so prepared has been studied. Observations reveal that the crystallinity of the films increases with the increase in substrate temperature. The scanning electron micrographs of the films show an increase in grain size with increasing substrate temperature. Crystallites as large as 1.8 µm has been observed in case of films deposited at 563 K. It has been observed that the carrier concentration and Hall mobility of films increases with increase in substrate temperature while resistivity decreases. The results indicate that the films are p-type, thus indicating holes as dominant charge carriers. Analysis of optical spectra of the films in the range 300-1100 nm show an allowed direct transition near the fundamental absorption edge (Eg1) in addition to a transition originating from crystal field split levels (Eg2). |
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10:30 AM |
H3-1-7 Mechanism of High Density Plasma CVD Phosphosilicate Glass Process without In-situ Plasma Chamber Clean
Y.L.. Wang (Taiwan Semiconductor Manufacturing Co., Ltd, Taiwan, R.O.C.); J.K. Lan (Taiwan Semiconductor Manufacturing Company, Ltd., Taiwan, R.O.C.); Y.L. Wu (Nation Chi-Nan University, Taiwan, R.O.C.); K.Y. Kuang, C. Ay (National Chia Yi University, Taiwan, R.O.C.) The high-density plasma phosphosilicate glass (HDP-PSG) has been studied for pre-metal dielectric.1-2 The benefits for using PSG include no post-deposition reflow, better gap fill capability, and better yield performance.1 The wafer process algorithm in the HDP-PSG tool included film deposition and post plasma clean. The post plasma clean was used to remove the plasma sub-product buildup on the chamber walls and internal fixtures.3-4 After in-situ clean, the system can be returned to a baseline condition in preparation for subsequent wafers. However, the deposition-clean cycle did heavily impact the throughput. This research explored the feasibility of changing the clean frequency from once per one wafer to once per three wafers. The mass transport phenomena for the HDP-PSG deposition was studied. The comparison in phosphorous concentration(P%), stress, and thickness for 1st, 2nd, and 3rd wafers were studied. The P% was measured by x-ray diffraction (XRD) method. The film qualities of 2nd and 3rd wafers were comparable and different to those of 1st wafer. The 1st wafer had 0.1% higher P% than 2nd and 3rd wafers. The HDP-PSG film thickness was 10~15 nm thicker on 1st wafer than on the others. The stress of 1st wafer was the highest. These variations in the film qualities were caused by the out-gassing from chamber walls. A throttle valve was used to control the deposition pressure. The throttle valve steps kept fixed number during 1st wafer deposition but became variable for 2nd or 3rd wafer. This phenomenon exhibited that the total gas quantities for 2nd or 3rd wafer deposition were more than that for 1st wafer. The secondary ion mass spectrometry (SIMS) analysis displayed that the phosphorous quantity in 2nd and 3rd wafers were lower than that in 1st wafer. The residual gas analysis (RGA) was used to monitor the out-gassing. A mass transport model for the HDP-PSG deposition was derived. |
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10:50 AM |
H3-1-8 Oxide Mediated Epitaxy Salicide Formation on Different Dopant Type of Si Surface
Y.M. Chen (Taiwan Semiconductor Manufacturing Co., Ltd., Taiwan, R.O.C.); Y.L.. Wang (Taiwan Semiconductor Manufacturing Co., Ltd, Taiwan, R.O.C.); J.J. Chang (National Chiao-Tung University, Taiwan, R.O.C.); M. Cao (Taiwan Semiconductor Manufacturing Co., Ltd, Taiwan, R.O.C.); G.C. Tu (National Chiao-Tung University, Taiwan, R.O.C.) Oxide-mediated epitaxy (OME) has shown promise as a technique for the formation of epitaxial CoSi2.. In this study, different chemical were applied to grow chemical oxide on different heavily doping Si surface and the effect of different chemical oxide to the OME were investigated. Both the oxide thickness and quality varied by different chemical and dopant and results in different salicide formation thickness. Thus, the junction leakage current also show different performance. With optimized type of chemical oxide and anneal temperature, the lowest junction leakage current can be achieved. |
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11:10 AM |
H3-1-9 Investigation of Electro-plating Voltage Effect on the Copper Electrodeposition Technology
K.W. Chen (National Chiao-Tung University, Taiwan, R.O.C.); Y.L.. Wang (Taiwan Semiconductor Manufacturing Co., Ltd, Taiwan, R.O.C.); Y.L. Wu (Nation Chi-Nan University, Taiwan, R.O.C.); C. Ay (Nation Chia Yi University, Taiwan, R.O.C.) The electro-plating process is very important for the copper gapfill capability beyond 0.13um technology. In general, the chemical additives in the plating bath have been reported for the optimization of superfilling VIA and over-plating reduction on high dense area of the metal array. All include the diffusion simulation of the accelerator and suppressor for VIA filling, and the planarization or inhibition of over-plating from the leveler. But these additives for the filling and planarization behavior would be affected from electro-plating voltage. This paper tends to study the correlation of electro-plating voltage and these additives. Besides, the plating film quality would be investigated on the impurity, stress, and resistivity. In advance, the information explains the filling limitation and side effect on the pattern density. While the understanding of voltage and chemicals control, it can help to promote the plating performance and reduce the void defect on the VIA bottom, even to achieve the yield improvement. |
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11:30 AM |
H3-1-10 Integration Solution for Dishing & Erosion Elimination in Copper Process beyond 0.13 um Technology
Y.L.. Wang (Taiwan Semiconductor Manufacturing Co., Ltd, Taiwan, R.O.C.); K.W. Chen (National Chiao-Tung University, Taiwan, R.O.C.); Y.L. Wu (Nation Chi-Nan University, Taiwan, R.O.C.); C. Ay (Nation Chia Yi University, Taiwan, R.O.C.) From aluminum to copper technology, copper plating and copper-CMP would be very important roles in Cu process. The bottleneck of copper technology would not maturely control the dishing and erosion performance between different metal pattern densities. However, the dishing and erosion do impact the metal resistivity distribution and uniformity control. The issue also results to the worse copper resistivity control than aluminum's. From the issue, the paper tends to provide the integrated solution in dishing and erosion elimination under Cu plating and CMP process. This work is to start-up from the copper process integration study to the dishing and erosion performance improvement in Cu-CMP. The methods included with ECP plating and CMP polishing slurry to optimize the planarization efficiency in dual damascene scheme. In ECP plating, the additives of bath have been investigated about 3-component chemicals performed better planarization than 2-component ones. Besides, the plating current would also affect the planarization relative to higher density pattern. In Cu-CMP slurry, it would be major factor to impact the dishing and erosion performance. Hence, the slurry is developed with organic passivation argent to eliminate the dishing and erosion performance. The passivation mechanism would be a key assumption in the paper. To sum up, these methods would provide more other benefits, such as resistivity deviation from 30% to <10%, over five times overpolish window (This performance would be correlative to dishing depth from original 1500A to >300A at 100x100um metal pad, and better EM/SM and higher 10% yield improvement. |