ICMCTF1998 Session H6: Interconnect Integration

Monday, April 27, 1998 1:30 PM in Sunrise Room

Monday Afternoon

Start	Invited?	Item
1:30 PM	Invited	H6-1 Integration of Dual Damascene Metallization W. Cote (IBM Microelectronics)
2:10 PM	Invited	H6-3 Polymer Low "k" Inter Layer Dielectric (ILD) Materials; Properties, Processing and Some Integration Benefits / Challenges. M.E. Mills, EO Shaffer, P Townsend (The Dow Chemical Company) The Microelectronics Industry will integrate polymer Low "k" ILD materials into the upcoming BEOL process generations in conjunction with both current interconnect metallurgy schemes and newer lower resistivity interconnect metal schemes as one response to device performance challenges. There is a strong potential for integration into current process generations (0.35/0.25 um) if the polymer ILD material exhibits a combination of sufficient thermal stability and process simplification characteristics to warrant these efforts. Several integration schemes must be considered for implementation into IC product roadmaps; polymer Low 'k" with existing interconnect metals (all Al or CVD-W and Al) and polymer Low "k" with new interconnect metals (Cu or Al) by Damascene. Each process integration sequence will require a unique combination of material, electrical, and integration properties from the Low "k" polymer ILD material. Recent announcements by IBM and Motorola indicate an acceleration of Cu implementation in commercial IC manufacturing. SEMATECH recently announced the successful Damascene integration of Cu in a Low "k" polymer ILD material, thereby addressing both the R and the C of the RC delay currently challenging high performance BEOL circuit designs. Low "k" polymer ILD materials are applied primarily by spin on methods, similar to photoresist processing, although some candidate materials are available applied by CVD or PECVD. After the application of the polymer ILD material the subsequent integration steps of oxide/nitride deposition, etching, PR removal, liner metal deposition, via/line metal deposition and CMP must all be achieved for successful integration prior to reliability testing. All Low "k" polymers can not be processed with similar recipes, making direct comparisons difficult and very time consuming. Dow Chemical's portfolio of Low "k' polymer ILD materials, which includes SiLK*, Cyclotene ^TM 5021 (BCB), and PFCB, offers a choice of different integration schemes with individual material related benefits and challenges. The material properties, common and specific processing issues for these Low ''k" polymer ILD materials as well as other leading candidates will be discussed in the context of integration demonstrations; including gapfill and planarization, etching, metal liner and fill deposition and CMP
3:30 PM	Invited	H6-7 Integration of Aluminum in Advanced DRAM Metallization Structures L. Gignac (IBM-T.J. Waston Research Center); K.P. Rodbell (IBM-T.J. Watson Research Center); L. Clevenger, R.C. Iggulden (IBM-Microelectronics); R.F. Schnabel, S.J. Weber, M. Hoinkis (Siemens); P.W. DeHaven (IBM- Analytical Services) In this paper, a novel process for producing 0.18 μm wide dual damascene Al lines with an aspect ratio of 4.5 will be described. Excellent fill of fine line width, high aspect ratio trenches was obtained by first depositing Ti/TiN liner films in damascene structures followed by Al reflow sputtering at temperatures greater than 350 °C. Though the liner films aided in Al trench fill, they reacted with Al during high temperature deposition to produce a high resistance phase, TiAl₃. TiN was found to prevent aluminide formation at deposition temperatures < 410 °C, but the quality of the barrier depended on the film step coverage and microstructure. The ability of the TiN barrier to prevent TiAl₃ formation was found to be crucial for achieving both low resistance lines and enhanced reliability. A matrix of films was analyzed using x-ray diffraction (XRD), transmission electron microscopy (TEM), and in situ resistance measurements during high temperature anneals to compare the barrier quality of chemical vapor deposited (CVD) TiN with physical vapor deposited (PVD) TiN. This experiment consisted of blanket films of Ti/TiN/CVD Al/reflow Al-Cu, where the TiN film was either CVD or PVD with a thickness of either 2.5, 5, or 10 nm. Results showed that, for a comparable film thickness, PVD TiN reacted at lower temperatures than CVD TiN with an activation energy for TiAl₃ formation of 2.6eV for PVD TiN and 2.4 eV for CVD TiN.
4:10 PM	Invited	H6-9 Dual Inline Copper Based Interconnects for Sub 0.25 μm Technology E. Weitzman (Motorola)
4:50 PM	Invited	H6-11 CMOS ULSI Technology with Copper Interconnections D.C. Edelstein (IBM Microelectronics) Recently, IBM announced the first technology to use copper interconnects on silicon integrated circuits, to be manufactured on its high-performance 0.2 μm ULSI CMOS chips with 6 levels of copper wiring starting this year. Features of this technology will be presented, including defining parameters, process integration, yield, and parametric data from fully-integrated wafers and functional SRAM and microprocessor packaged modules. To reach this level, extensive yield, reliability, and stress testing had to be passed successfully. Examples of these data on the wiring, devices, and circuits show results that, in all areas, meet or exceed the standards set by our current Al(Cu)/W-stud CMOS wiring technology. In certain areas such as electromigration and stressmigration, copper wiring shows fundamentally large advantages. Other tests such as thermal cycling and temperature/humidity stressing indicate no device leakages associated with copper poisoning, and no anomalies that would indicate weaknesses in the integrated build. This work demonstrates that the problems long-discussed for integrating copper wiring on Si chips can be overcome, to make reliable, properly-functioning chips with a high-yield, low-cost, and extendable process.