AVS2015 Session EM+NS+PS-MoM: More Moore! Materials and Processes to Extend CMOS Another Decade

Recently Ⅲ-Ⅴ compound materials have attracted significant attention as promising channel materials for sub-10 nm logic MOSFET due to their high mobility. GaSb is a strong candidate for pMOSFETs because of its high hole mobility in addition to the insolubility of its native oxides. Even with the outstanding electrical properties of GaSb, there are some drawbacks related to the instability of its native oxides and metallic layer of elemental Sb. The native oxides and metallic layer of elemental Sb are considered to be sources of Fermi level pinning and flat C-V curves. Therefore, it is necessary to improve surface treatment methods. Since it is possible to eliminate its native oxides and elemental Sb by heating them, it is essential to research temperature related surface treatments.

In this study, various ALD temperatures from 190 ^oC to 310 ^oC and pre-RTP(Rapid Thermal Process), which is first introduced here as a pre-deposition treatment, have been adopted for eliminating the remaining native oxides after cleaning. N₂ gas atmosphere is used to suppress the oxygen to interact with GaSb surface for the pre-RTP. GaSb metal-oxide-semiconductor capacitors were fabricated on p-type GaSb, which has a carrier concentration of 1.0~2.0 x 10¹⁷ cm^-3. GaSb was degreased with acetone, ethanol, and isopropane for 5 minutes each and then etched by HCl. 10 nm of Al₂O₃ has been deposited as a gate dielectric with TMA and DI water by thermal ALD. For the metal gate, a Pt electrode has been deposited with an electron-beam evaporator.

When the deposition temperature increases, the Ga₂O₃ peak increases and the substrate peak decreases under XPS analysis. It is observed that the amount of Sb increases at the GaSb/Al₂O₃ interface as the deposition temperature increases in AES depth profiles. Both Ga2O3 and elemental Sb have increased generation as the deposition temperature increases, since the surface chemical reactions are accelerated by increased temperature. The CV curve becomes flat as the deposition temperature increases. It indicates that Ga₂O₃ has a flattening effect of the CV curve and the more amount of Ga₂O₃ that is generated, the flatter the CV curve will become.

Desorption of the native oxides and elemental Sb should occur by annealing the substrate. After the pre-RTP, the amount of elemental Sb increases, since the remaining native oxide, after cleaning, is reduced by increased temperatures. The remaining native oxide Sb₂O_3, after cleaning, supplies oxygen to the substrate and becomes elemental Sb. The leakage current increases with pre-RTP. It shows that the elemental Sb increases the leakage current. Further study on optimizing pre-RTP conditions is needed.

For future high performance III-V n-channel MOS devices, In_0.53Ga_0.47As is a promising material for the channel due to its high electron mobility. Atomic layer deposited (ALD) Al₂O₃ has a large conduction band offset to InGaAs and can form a low defect-density interface with InGaAs [1]. ALD-HfO₂ can achieve a very low EOT (effective oxide thickness) with low gate leakage [2]. Therefore, both of these oxides have received extensive attention as candidate dielectric layers for InGaAs nMOSFETs. Apart from the well-known oxide/InGaAs interface charge traps that may pin the Fermi level of the channel, traps in the oxide layer, called border traps, may also reduce the charge in the channel and thus degrade the on-state performance of InGaAs MOSFET devices. We report a study of the effects of various approaches to reduce the density of border traps (N_bt), such as variation of the ALD temperature, and of post-gate metal forming gas (5% H₂/95% N₂) anneal (FGA) conditions.

Experimental methods employed include quantitative interface trap and oxide trap modeling [3, 4] of MOS capacitor data obtained over a range of frequencies and temperatures. We find that MOS capacitors fabricated using trimethylaluminum (TMA)/H₂O at an ALD temperature of 120°C have a considerably lower border trap density while maintaining a low interface trap density (D_it) compared to samples prepared with a more standard 270°C Al₂O₃ ALD temperature. It is also found that large-dose (~6,000 L) exposure of the In_0.53Ga_0.47As (100) surface to TMA immediately after thermal desorption of a protective As₂ capping layer in the ALD chamber is an important step to guarantee the repeatability of high quality Al₂O₃/InGaAs samples made at Al₂O₃ ALD temperatures much lower than 270°C. The reduction of N_bt is consistent with time-of-flight secondary ion mass spectrometry depth profiles that show more effective hydrogen incorporation in the low-temperature ALD-grown Al₂O₃ films during post-gate FGA.

The N_bt of Al₂O₃ under various conditions will be compared with that of low-temperature ALD-grown HfO₂ films on InGaAs substrates. For the HfO₂ case, we also confirm the independence of border trap response on the electrical measurement temperature and check the influence of the crystal orientation of the InGaAs surface on MOS interface characteristics.

This work was supported by the US-Israel Binational Science Foundation.

References

[1] J. Ahn et al., Appl. Phys. Lett. 103 (2013), 071602

[2] V. Chobpattana et al., J. Appl. Phys. 114 (2013), 154108

[3] H. Chen et al., IEEE TED 59 (2012), 2383-2389

[4] Y. Yuan et al., IEEE TED 59 (2012), 2100-2106

A broader range of channel materials allowing better carrier confinement and mobility could be employed if a universal control monolayer (UCM) could be ALD or self-limiting CVD deposited on multiple materials and crystallographic faces. Si-OH is a leading candidate for use as the UCM, as silicon uniquely bonds strongly to all crystallographic faces of InGa_1-xAs, In_xGa_1-xSb, In_xGa_1-xN, SiGe, and Ge enabling transfer of substrate dangling bonds to silicon, which may then subsequently be functionalized with an oxidant such as HOOH(g) in order to create the UCM terminating Si-OH layer. This study focuses on depositing a saturated Si-OH seed layer on InGaAs(001)-(2x4) at a substrate temperature of 350°C. XPS in combination with STS/STM were employed to characterize the electrical and surface properties of the saturated Si-OH seed layer on InGaAs(001)-(2x4).

The 350°C self-limiting CVD procedure includes a decapped In_0.53Ga_0.47As(001)-(2x4) surface dosed with total 87.6 MegaLangmuir Si₂Cl₆ followed by 210.55 MegaLangmuir total anhydrous HOOH(g). Complete saturation of silicon coverage is determined to occur once further dosing with Si₂Cl₆ leads to no further increase in the silicon 2p or further decrease in the substrate gallium 3p peak areas. Complete surface saturation of Si-O_x on InGaAs(001)-(2x4) was determined to occur once no further increase in the O 1s peak was seen with additional anhydrous HOOH(g) doses. Following Si-OH surface saturation, 300,000 L TMA was dosed at 250°C, and XPS shows the emergence of Al 2p and C 1s peaks indicative of TMA surface nucleation. The surface was then dosed with 500 L atomic H at 250°C to remove the methyl groups on the surface aluminum and replace with -H termination as well as remove any residual chlorine left on the surface. The surface was then exposed to air for 30 minutes, dosed with an additional 500 L atomic H at 250°C, and then STS measurements were performed. STM measurements of the Si-O_x surface show uniform surface coverage. STS measurements show the surface Fermi level position moves towards midgap due to a surface dipole formation from –OH groups and oxygen bonding to the surface. TMA dosed on the Si-O_x surface shifts the Fermi level back towards the conduction band, consistent with unpinning and the -OH induced surface dipole being lessened through surface bonding with dimethylaluminum groups. Following hydrogen dosing and air exposure, the surface Fermi level remains near the conduction band edge consistent with the surface being stable and unreactive in air. Preliminary MOSFET studies on InGaAs(001) show equivalent performance with Si₂Cl₆ predosing compared to in-situ cleaning with atomic H.

The last decade has seen nearly exponential growth in the science and technology of two-dimensional materials. Beyond graphene, there are a variety of layered materials that provide a broad range of electronic characteristics useful for transistors, flexible electronics, sensors, and photodetectors, to name a few. However, bridging the gap between science and teechnology often lies in one’s ability to synthesize materials on the wafer scale (or bigger). In this talk, I will discuss recent breakthroughs for direct growth of two-dimensional atomic layers and heterostructures with scalable techniues such as metal-organic chemical vapor deposition. We have demonstrated the direct growth of MoS₂, WSe₂, MoS₂/WSe₂, and hBN on epitaxial graphene to form large area van der Waals heterostructures. We reveal that the properties of the underlying substrate dictate properties of the layers and heterostructures, and that the direct synthesis of TMDs on epitaxial graphene exhibits atomically sharp interfaces. Our work has lead to a better understanding of vertical transport in 2D heterostructures, and we have identified new phenomenon in multi-junction heterostructures that has lead to resonance tunneling between layers and ultimately negative differential resistance.

1. Eichfeld, S. M.; Hossain, L.; Lin, Y.-C.; Piasecki, A. F.; Kupp, B.; Birdwell, A. G. G.; Burke, R. A.; Lu, N.; Peng, X.; Li, J.; et al. Highly Scalable, Atomically Thin WSe2 Grown via Metal-Organic Chemical Vapor Deposition. ACS Nano 2015.

2. Y.C. Lin, C.-Y. Chang, R. Ghosh,J.Li, H.Zhu, R.Addou, B.Diaconescu, T.Ohta, X.Peng, N.Lu, M.J. Kim, J.T. Robinson, R.M.Wallace, T.Mayer, S.Datta, L.J. Li, J.A. Robinson; Atomically Thin Heterostructures based on Single-Layer Tungsten Diselenide and Graphene; Nano Letters

3. M. S. Bresnehan, G. Bhimanapati, K. Wang, D.Snyder, J.A.Robinson; Impact of Copper Overpressure on the Synthesis of Hexagonal Boron Nitride Atomic Layers; ACS Appl. Mater. Interfaces, 6, 16755–16762 (2014)

4. S.M. Eichfeld, C.M. Eichfeld, Y.C. Lin, L. Hossain, J.A. Robinson; Rapid, non-destructive evaluation of ultrathin WSe2 using spectroscopic ellipsometry; APL Materials 2 (9), 092508

5. Y.C. Lin, N. Lu, N. Perea-Lopez, J. Li, C.H. Lee, Z.Lin, P.N. Browning, M.S. Bresnehan, L. Calderin, M.J. Kim, T.S. Mayer, M. Terrones, J.A. Robinson; Direct Synthesis of van der Waals Solids on Epitaxial Graphene; ACS Nano 8 (4), 3715-3723 (2014)

The three pillars in semiconductor device technologies are (1) the p-n diode, (2) the MOSFET and (3) the Bipolar Junction Transistor (BJT). They have enabled the unprecedented growth in information technology that see today. For any new material, therefore, the development of these three devices is critical for providing benchmark performance against highly scaled Si-based technologies. Here, we will describe our efforts to fabricate and characterize these three benchmark devices in 2D materials, including graphene and transition metal dichalcogenide semiconductors (TMDs).

Although graphene is gapless, we will describe device concepts based on graphene p-n junctions that can lead to steep subthreshold slope devices. Critical to realizing such devices is the demonstration of relativistic Klein tunneling, a property of chiral carriers that arise from the unique electronic structure of graphene. Here, we will describe the fabrication and characterization of graphene p-n junctions, and discuss the unique tunneling properties that arise in these junctions and our efforts to realize high efficiency switching devices.

Using TMD materials, we have fabricated a single device that can reconfigure into p-n, MOSFET, and BJT devices. The reconfigurable device allows us to provide fundamental linkages between material properties and device performance not possible by fabricating the three devices individually. We will provide our method of fabrication and describe electrical and optical properties of the reconfigurable device.

Vertical heterostructures consisting of atomic layers separated by insulators can open a window to explore the role of electron interaction in these materials, otherwise not accessible in single layer samples, as well as to explore device applications.

We describe here the realization of vertical heterostructures consisting of graphene, hexagonal boron nitride (hBN), and transition metal dichalcogenides realized using a layer-by-layer transfer. In double bilayer graphene heterostructures separated by hBN dielectric [1] where the two layers are rotationally aligned the interlayer tunneling current measured as a function of interlayer bias reveals a gate-tunable resonance thanks to momentum conserving tunneling. [2, 3] We discuss potential device application based on these experimental observations, as well as metrics that allow a benchmarking of their performance.

We also discuss the realization and characterization of graphene-MoS₂ heterostructures, which reveal a strong negative compressibility in the MoS₂ layer as a result of electron-electron interaction. [4]

Work done in collaboration with Kayoung Lee, Babak Fallahazad, Sangwoo Kang, Stefano Larentis, Hema C. P. Movva, Sanjay K. Banerjee, Leonard F. Register, Takashi Taniguchi, and Kenji Watanabe, and with support from the NRI-SWAN Center, Office of Naval Research, and Intel Corp.

[1] “Chemical potential and quantum Hall ferromagnetism in bilayer graphene”, K. Lee, B. Fallahazad, J. Xue, D. C. Dillen, K. Kim, T. Taniguchi, K. Watanabe, E. Tutuc, Science 345, 58 (2014).

[2] “Gate-Tunable Resonant Tunneling in Double Bilayer Graphene Heterostructures”, B. Fallahazad, K. Lee, S. Kang, J. Xue, S. Larentis, C. Corbet, K. Kim, H. C. P. Movva, T. Taniguchi, K. Watanabe, L. F. Register, S. K. Banerjee, E. Tutuc, Nano Letters 15, 428 (2015).

[3] “Bilayer Graphene-Hexagonal Boron Nitride Heterostructure Negative Differential Resistance Interlayer Tunnel FET”, S. Kang, B. Fallahazad, K. Lee, H. C. P. Movva, K. Kim, C. Corbet, T. Taniguchi, K. Watanabe, L. Colombo, L. F. Register, E. Tutuc, S. K. Banerjee, IEEE Electron Device Letters 36, 405 (2015)

[4] “Band Offset and Negative Compressibility in Graphene-MoS₂ Heterostructures”, S. Larentis, J. R. Tolsma, B. Fallahazad, D. C. Dillen, K. Kim, A. H. MacDonald, E. Tutuc, Nano Letters 14, 2039 (2014).