AVS2013 Session EM-MoA: High-k Gate Oxides for High Mobility Semiconductors II

The silicon counterpart of graphene, the so called “silicene” [1,2], has been so far a theoretical option but its synthesis constituted a formidable challenge. Nonetheless, recent efforts have moved up this fascinating hypothesis to a concrete evidence [3][4] thus triggering a tremendous interest in silicene for electronic applications and fundamental investigations.

Non-trivial atomic arrangements of the silicene are expected to occur which are dictated by a delicate balance between planar and buckled bonding . Indeed, due to the large ionic radius of silicon, silicene is naturally prone to occur with a variety slightly-buckled configurations which can be driven by the silicene/substrate local interactions [1]. This structural complexity discriminates the experimentally observed silicene from graphene, and it is expected to bring basically new physical properties such as topological phase transitions, quantum spin Hall effect, or band gap opening [5]. Here we report on recent experimental results showing the formation of 2D epitaxial silicene on Ag(111) substrates [4] based on in situ scanning tunnelling microscopy-spectroscopy investigations.

Despite its structural flexibility, silicene is technologically limited by its chemical instability. Indeed, silicene undergoes oxidation when exposed to dry air. Then, interfacing silicene with a gate dielectric is essential for any feasible voltage bias application but also to barely save it from possibly destructive reactivity in ambient conditions.

While disentangling silicene from metallic templates is still an open challenge, on-top interface engineering of silicene is here addressed with the goal to develop a non-reactive encapsulation process. This effort enabled us to fabricate a chemically stable Al₂O₃/silicene/Ag heterostructure through a carefully tailored co-deposition of Al and O₂ [6]. Raman spectroscopy was then used to demonstrate the structural stability of the encapsulated silicene. Finally, new hints at Si nanosheets grown on ad hoc 2D material templates are also discussed aiming at the silicene “portability” for device-oriented exploitation.

These outcomes disclose exceptionally novel issues in the physics of the emerging silicene and promote a renewed interest in nanoscaled silicon as active material for electronic devices.

References

1. S. Cahangirov, et al, Phys. Rev. Lett. 102, 236804 (2009).

2. M. Houssa, et al., Appl. Phys. Lett., 97, 112106 (2010).

3. P. Vogt, et al., Phys. Rev. Lett. 108, 155501 (2012).

4. D. Chiappe, et al., Adv. Mater. 24, 37, 5088 (2012).

5. M. Ezawa, Phys. Rev. Lett. 109, 055502 (2012).

6. A. Molle, et al., Adv. Func. Mat. 2013, 10.1002/adfm.201300354 (just accepted).

Germanium has long been considered as a replacement channel material due to its higher intrinsic hole mobility compared to silicon and its relative compatibility with current CMOS processing. Growth of Ge channel materials on bulk Si would be ideal for minimizing cost and allow for the continued use of current manufacturing tools. Ge grown on Si, however, results in a significant defect density due to the 4.2% lattice mismatch, reducing device performance.

In this work, we study the fabrication of tri-gate Ge MOSFETs, grown by MBE, on Si using Aspect Ratio Trapping (ART) ^1,2 to reduce the Ge defect density. ART is a growth technique that allows for the reduction of defects for lattice mismatched materials by trapping the threading dislocations into the sidewalls of patterned nanoscale trenches in which the epitaxial growth takes place. This technique has the added benefit of producing the necessary geometric structure required for highly scaled tri-gate devices, alleviating short channel effects, while simultaneously reducing defect density. The fabrication of high aspect ratio (>2) trenches in SiO₂ for epitaxial growth of Ge will be discussed as well as the issues and solutions associated with the inherent non-selectivity of solid-source MBE growth. TEM, SEM, and AFM are employed to characterize the growth quality and assess the various device fabrication steps.

Tri-gate MBE-grown Ge MOSFETs on Si are fabricated using a gate first process. A high-quality Ge interfacial region is obtained by a surface functionalization technique using 50 pre-pulses of DI-H₂O in an ALD chamber at 250°C, followed by a 2 nm thick interfacial Al₂O₃ deposition at 250 °C followed by a forming gas anneal (FGA) at 350 °C.³ The FGA step converts the functionalized surface to a thin layer of GeO₂, improving the electrical characteristics of the devices. 2.5 nm of HfO₂ is then deposited by ALD followed by a 500 °C post-deposition anneal in N₂. 150 nm of reactively sputtered TiN is deposited as the gate metal. Schottky junction source and drain regions are formed by sputtering 20 nm of Pt, capped with TiN, and annealed at 400 °C to form PtGe₂.⁴ A final 350 °C FGA completes the device processing. Detailed electrical characterization, using a suite of techniques, was performed and correlated with the MBE growth and gate stack formation.

This work is sponsored in part by the SRC Global Research Corporation.

1 T. A. Langdo, et al., Appl. Phys. Lett. 76, 3700 (2000).

2 J. Bai, et al., Appl. Phys. Lett. 90, 101902 (2007).

3 S. Swaminathan, et al., J. Appl. Phys. 110, 094105 (2011).

4 R. Li, et al, IEEE EDL, 27, 476 (2006).

Equivalent oxide thickness (EOT) scaling is one of the most critical challenges for future Ge-MOSFET technology. It is difficult to achieve sub-1 nm EOT with a single dielectric material, due to the intrinsic trade-off between dielectric constants and band gaps. Recently, bilayer high-k materials, such as TiO₂/Al₂O₃, HfO₂/Al₂O₃, have been paid increasing attention. However, there are several challenges remaining for bilayer high-k stacks on Ge substrate: 1) an ultra-thin high-quality GeO₂/GeO_x layer is generally reported to be necessary for effective Ge surface passivation, but this is difficult to obtain by routine thermal oxidation. It has been reported that processes such as post-dielectric deposition plasma oxidation are beneficial for preparing such interface layers. 2) The interface between the two high-k materials in the bilayer must be abrupt and their thicknesses well-controlled, to reduce gate leakage as the EOT is scaled. In this paper, we address these challenges by a simple, low-temperature process flow using thermal annealing. Using carefully-controlled atomic layer deposition (ALD) of the dielectric layers and a forming gas anneal (FGA), a TiO₂/Al₂O₃/Ge gate stack is demonstrated with EOT = 0.63 nm that achieves low D_it and gate leakage current density in MOS capacitors. Pt gated Ge-pMOSFETs with TiO₂/Al₂O₃ gate stacks are fabricated, and have a sub-1nm EOT, 75 mV/dec subthreshold swing, 10m A/m m on state current and avoid gate metal/TiO₂ reaction or interdiffusion.

In our process, a high quality Al₂O₃ layer on the Ge substrate is grown by atomic layer deposition with the help of efficient sites for Al(CH₃)₃ precursor adsorption produced by oxidant pre-dosing the Ge(100) surface prior to ALD. Forming gas anneal (FGA) is found to be a critical step to realize low interface trap densities in low EOT Ge transistors. We observed great improvement of device performance after FGA on both MOSCAPs and MOSFETs, the effectiveness of FGA determined by Al₂O₃ thickness, FGA conditions, and the identity of the overlying gate metal.

We have used both hard and soft x-ray synchrotron photoemission electron spectroscopy (PES) to investigate the Al₂O₃/Ge interface and the TiO₂ layer in various Al₂O₃/Ge and Pt/TiO₂/Al₂O₃/Ge structures before and after FGA. An increase in intensity of the Ge+4 feature is observed after FGA of Al₂O₃/Ge samples, and emergence of a detectable Ti +3 peak, consistent with loss of oxygen during FGA, is also identified in Pt/TiO₂/Al₂O₃/Ge samples. Effects of these local chemical changes on the MOS performance of the resulting gate stacks will be discussed.

Si CMOS scaling is reaching practical and fundamental limits. Currently, use of strain engineering to boost mobility is the dominant technology for high performance Si MOSFETs. However, mobility boosting by straining Si will also saturate with future scaling. Therefore, looking into future it becomes important to look at higher mobility materials like Ge and III-Vs to continue scaling of MOSFETs. For these materials to become main-stream several problems need to be solved, including surface passivation. In this talk we will present our recent results on passivation of Ge, GeSn and III-V antimonides.

Ge and GeSn have recently emerged as promising candidates not only for high performance CMOS but also for optoelectronics. Ge PMOS with several different high-k dielectrics have been demonstrated with excellent performance. Ge surface passivation with GeO₂ shows low D_it near valance band (E_v). However, Ge NMOS have so far exhibited poor drive current. This is partially attributed to high D_it near the conduction band (E_c). In recent work we have achieved low and symmetric D_it through sulfur passivation followed by ALD of Al₂O₃ and then annealing in ozone. With these two treatments, a record-low D_it (<1E11/cm²eV) at both band edges is achieved

In GeSn with increasing Sn content G valley comes down with respect to the indirect valleys, increasing population of electrons in this low electron mass valley which boosts mobility. A novel surface passivation scheme using ozone oxidation of thin Ge cap has been demonstrated with record low D_it of 3E10¹¹/cm²eV at high-ĸ/GeSn interface.

While there have been many demonstrations on n-channel MOS in III-V semiconductors showing excellent electron mobility and high drive currents, hole mobility in III-V p-channel MOS has traditionally lagged in comparison to Si. GaSb is an attractive candidate for high-performance III-V pMOS due to its high hole mobility. Performance degradation due to interfacial traps is generally considered one of the main challenges for III-V MOSFETs. We have demonstrated passivation of GaSb with an ALD Al₂O₃ gate dielectric with a midband-gap D_it of 3E10¹¹/cm²eV and demonstrated excellent pMOSFETs.

We have further investigated the suppression of interface state response using band engineering in III-V quantum well MOSFETs and experimentally verified the concept in antimonide compounds system using a gate-stack consisting of Al₂O₃/GaSb/InAlSb. It is shown that if the thickness of the interfacial layer of GaSb is scaled down to a few monolayers, the effective bandgap of the interfacial layer increases dramatically due to quantum confinement, which leads to the suppression of interface-trap response.

Silicon-germanium is a promising candidate for potential channel or contact materials due to its higher hole and electron mobility. To minimize the oxide-semiconductor interfacial defect density, a chemical and electronic passivation layer must be formed before the oxide layer is deposited. In this study, a monolayer of H₂O or H₂O₂ chemisorbates is shown to activate Trimethylaluminum (TMA) chemisorption due to the Si/Ge-OH bonds catalyzing the formation of an ultrathin passivation layer which can serve as an ideal ALD nucleation template on SiGe. However, since H₂O chemisorption results in equal density of Si/Ge-H and Si/Ge-OH sites on the SiGe(100), H₂O can only provide a maximum of 0.5 monolayer of Si/Ge–OH sites, limiting the TMA nucleation density. By using H₂O₂ dosing, the density of Ge–OH sites can be doubled thereby increasing the potential TMA nucleation density. This study compares the passivation of the SiGe(100) surface via H₂O and H₂O₂, for the application of nucleating ALD growth on the surface, using scanning tunneling microscopy (STM), scanning tunneling spectroscopy (STS), and x-ray photoelectron spectroscopy (XPS).

Using a differentially pumped dosing system, a clean SiGe(100) sample was dosed at room temperature with a saturation dose of either H₂O or H₂O₂. STM and XPS measurements indicate that H₂O₂ dosing leaves the SiGe(100) surface, which is mostly Ge atoms due to surface segregation, terminated with an ordered monolayer Ge-OH sites. A very small density of unreacted atoms are left unpassivated on the surface and have half filled dangling bond states causing a large local amount of conduction band edge states in the bandgap. STS measurements of the Ge-OH sites show the conduction band edge dangling bond states are eliminated due to the passivating Ge–OH bonds, but the Fermi level is pinned near the valence band edge due to the large surface dipole . When the surface is annealed to 310°C, XPS measurements indicate that the –OH species on the surface break bonds with the Ge atom and bond instead to the Si atoms, raising Si atoms towards the surface. XPS also verifies that no oxygen leaves the surface due the 310°C anneal. Instead, the oxygen remains on the surface in the form on Si-OH or SiO_x species. It is hypothesized that a lower temperature anneal would prevent SiO_x species from forming, leaving a surface which is only terminated by Si-OH bonds which would serve as an ideal template for ALD nucleation of TMA for Al₂O₃ growth. STS measurements show that TMA nucleation on the H₂O₂ functionalized SiGe(100) surface unpins the Fermi level and has a wide bandgap with no band edge states demonstrating very good interface quality.