AVS2011 Session PS-MoM: Advanced FEOL / Gate Etching I

Plasma etch processes are the only technological solution to address the critical dimension control at the nanometer range imposed by the continuous downscaling of CMOS device dimensions in microelectronics. However, the current processes are reaching their limits of controlling etch selectivity, defects, critical dimensions and uniformity. Lately, pulsed plasmas are increasingly used to overcome some of these limitations. On the basis of HBr/O₂ plasmas, dedicated to STI (Shallow Trench Isolation) etching, we discuss the role of the pulse parameters regarding the etched profiles, the reactive etch layer, the uniformity and the passivation layer. To investigate the passivation layer at various trench depths and CDs we developed a new XPS technique for quasi in-situ chemical topography analysis.

The experiments are carried out in a 300 mm AdvantEdge^TM tool from Applied Materials Inc. The two generators to sustain the plasma (ICP) and to polarize the wafer (CCP), operated at 13.56 MHz, have been modified with the Pulsync^TM system to allow pulsing at a wide range of parameters. However, only synchronous pulsing is studied here. Moreover, a Theta300 angle resolved XPS system from Thermo VG is connected under vacuum, allowing quasi in-situ analysis of an etched sample. Several additional diagnostic methods including time resolved UV-absorption, mass spectroscopy and ellipsometry are used to study the impact of pulsing the plasma on the surface and the gas phase compared to a continuous wave process.

We demonstrate that plasma pulsing can minimize the mask faceting and consumption which is due to a change in the ion energy distribution and the presence of larger molecular ion species. The duty cycle controls the formation of the passivation layer that governs in turn the form of the etched profiles. This correlation can partly be explained by less dissociated oxygen molecules in low duty cycle pulsing. Nevertheless, XPS analyses show that the chemical composition of the passivation layer changes little with height and trench CD while its thickness is directly linked to the aspect ratio of the analyzed part of the sidewall. Less thickness variation with respect to the aspect ratio is observed in pulsed mode, which explains an improved local uniformity in profile evolution. Furthermore, the time compensated etch rate with respect to the actual ON time of the plasma is increasing at low duty cycles due to a change of etch regime from more radical flux limited to ion flux limited. Nevertheless, the overall process etch rate is decreasing in pulsed mode which can be partly counteracted by increasing the source and the bias power.

The etching processes for integrated circuits fabrication becomes extremely challenging when the devices dimensions are downscaling and the etch process has to stop on the ultra thin layers (less than 2nm) of materials. Perfect control of the passivation layers and mask erosion are required to precisely control the patterns profiles, which necessitates using flows and energies of plasma species in ranges which can not be attainable with current plasma technologies. In addition, limiting the plasma induced damage to thin layers requires very low ion energies which are not accessible in current plasma technologies. One promising solution is to pulse the plasma in conventional industrial reactors at very low duty cycle. Using this solution, the ratio of radicals and ions as well as their energy can be fine tuned in ranges that are unreachable otherwise, and very low energy ions are produced which strongly minimizes the damage to the thin layers exposed to the plasma.

Experiments are performed on a 300mm diameter Inductively Coupled Plasma chamber commercialized by Applied Materials (DPSII G5) equipped with the pulsync system to enable plasma pulsing in an industrial reactor.

In this paper, we will show how plasma pulsing can be used to improve uniformity and pattern profiles by better controlling the passivation layer formed on the patterns sidewalls during the etching. In addition, we will demonstrate that the reduction of the average ion energy as well as the use of molecular ions decreases mask erosion, as well as damage to ultrathin etch stop layers. Morphological characterization, surface characterization and plasma diagnostics will be correlated to explain the mechanisms responsible for the process improvement.

Plasma etching of high-k materials, including HfO₂, has attracted much attention due to the necessity to integrate these materials in MOSFET transistor. After the metal gate patterning process, the high-k dielectric film must be removed from the source and drain regions of the transistor. It is today well established that HfO₂ can be etched selectively towards SiO₂ and Si in BCl₃/Cl₂ plasma. However, it remains difficult to minimize the plasma induced damages (Si amorphisation and recess) in the source/drain transistor regions in such processes. Since pulsed plasmas have shown a capability to minimize Si-recess in typical silicon gate oxide etching processes, we have investigated their potential for HfO₂ etching.

The experiments are performed in a 300mm DPS tool from Applied Materials. The chamber is modified to allow plasma diagnostic like UV-broad band absorption spectroscopy. The reactor is also connected to an Angle-Resolved X Ray Photoelectron Spectroscopy analyzer by a robotized vacuum chamber. The etching rate of HfO₂ sample (either 40 or 3.5nm-thick HfO₂ films with 8 Å SiO₂ interlayer deposited on Si substrates) and of SiO₂ samples (10 nm thick) are measured in real time by in situ multi-wavelength ellipsométrie.

We have evaluated the capability of pulsed plasmas to minimize the plasma induced damage of silicon during the etching of HfO₂ high-k gate dielectric. XPS analyses show that the perturbation of the bulk Si lattice is less pronounced with pulsed conditions, which is attributed to a lower ion bombarding energy. However, the formation of a BCl_x polymer selectively on the silicon (which is responsible for the HfO₂ to Si etching selectivity) is reduced when the plasma is pulsed leading to a loss of selectivity. VUV absorption spectroscopy indicates that the fragmentation of BCl₃ molecules, which leads to the formation of B-rich polymer precursors, decreases dramatically when the plasma is pulsed at low duty cycle. Therefore, as the duty cycle is reduced, the fluxes of B radicals to the wafer are reduced while the amount of Cl in the polymer increases. It follows that the polymer deposition rate drops, eventually leading to a loss of selectivity at the lowest duty cycles.

However, there are several ways to retrieve the process selectivity in pulsed plasma, such as reducing the BCl₃ flow in the gas mixture or working at higher pulsing frequencies (up to 10 kHz) to enhance B formation in the gas phase. Pulsing the plasma is not a magic knob since it strongly changes the range of allows news physics and chemistry ranges plasma parameters.

However, plasma pulsing reduces significantly the plasma induced damages after process optimization.

In CMOS technology, the downscaling of the transistor gate dimension, driven by ITRS roadmap specifications for advanced technology, requires the introduction of new materials. Dry etching step of those new “High-K Metal Gate” (HKMG) stacks is critical for the electrical performances of the devices and needs very accurate process control to achieve correct profiles, with a good Critical Dimension control. Moreover, characterization tools are now dealing with thin materials thicknesses sometimes around the limit of one full atomic layer. In this work we focus on dry etching process of 28nm technology High-K Metal Gate stacks. Several issues, especially for Metal/Capping layer interfaces, are investigated to better understand and control physicochemical interactions.

Most of etching experiments are carried out in a 300mm DPS AdvantageEdge^TM etch chamber from Applied Materials allowing in situ diagnostic, as reflectometry and spectroscopic ellipsometry. This modified tool permits to transfer wafer under vacuum to a customized Theta 300 XPS system from Thermo Fisher Scientific for quasi in-situ analysis without exposure to the environment. Samples were 300mm diameter Si wafer with full sheet and/or patterned deposited layers. Industrial 28nm photolithography & plasma etching process developed to gate first approach were employed.

Preliminary experiments have shown that foot and undercut effects are possible profiles deformations due to metallic interfaces, and we have to control these deviations.

Consequently, we focused first on the TiN/LaO interfaces which we highlight as a critical step. TEM analyses demonstrate that LaO capping layer acts as etch stop layer for current TiN etching chemistries. Therefore, a specific step for LaO removal is needed; otherwise etching residues are left over.

Layer thickness and step time in the specific removal of Lanthanum oxide are some parameters which directly impact the under-layer materials with the observation of pitting on nMOS open areas or residues on pMOS.

XPS characterizations were carried out. Etching results analyses for TiN/LaO/TiN interface reveal the fact that after the whole stack etching step, some LaO residues remain on the sample surface although TiN disappear as evidenced from XPS survey scan. The conclusion is that TiN looks totally removed as Lanthanum can be redeposit or for certain push-forward. Such as mechanisms were considered, and experiments were carried out to understand and complete this result.

Integration of thin metallic and capping layers in gate stacks challenge dry etching process. Those results highlight the trend of interactions all across the plasma etch process.

Wavelength and Numerical Aperture scaling in optical lithography have allowed CMOS density scaling to march along the Moore ’s Law curve for the past three decades. However, at the sub 22nm CMOS nodes, the print pitch faces a technological barrier at the 80nm mark for the Front, Middle and Back Ends of Line. Until further wavelength scaling becomes available through Extreme Ultraviolet (EUV), the industry’s attention is focused on Double Patterning. Multiple Interdigitated Lithography and Sidewall Image Transfer (SIT) are the two broad categories of techniques under consideration. Interdigitated Lithography can be subdivided into approaches with and without multiple passes through etch. Both of these techniques present unique etch challenges in assembling looser pitch patterns into a composite mask and subsequent pattern transfer into the stacks of interest. We will review etch perspectives on the applicability of double patterning methods to various levels in the process flow.

In particular, Fins for FinFET technology represent the tightest pitch (approximately 40nm for the technology nodes in development at this time) and yield well to Sidewall Image Transfer. We will present the issues surrounding mandrel definition and spacer film properties for Fin definition. The Gate level poses competing requirements of overlay control between the simpler patterns and the need to attain multiple Critical Dimensions (CDs) and pitches. We will examine this and the challenges of etch into advanced gate stacks for the 14nm node. At the Interconnect levels, we will consider the challenges of transferring not only trenches but also self aligned via patterns at sub -40nm half pitch into ultra low-k (ULK) dielectrics.

To continue scaling CMOS devices at the traditional pace following Moore’s law, high selectivity of etch processes towards multiple materials is approaching nanoscopic dimensions. The spacer etch process is a very critical element in the CMOS device process flow as it ensures and enables the electrical isolation of source/drain and gate regions. Extremely high precision is needed to form a silicon nitride (SiN) spacer without damaging exposed Si, SiO₂, or other surfaces (SiGe or SiC for example). This process is even more challenging for non-planar devices (such as FinFETs and Trigates), where the plasma process needs to be able to form the spacer on the gate sidewall, but not the fin sidewall. At the same time the exposed SiO₂ and Si surfaces (if applicable) have to withstand the extended processing necessary to form the spacer.

Multiple etch gas chemistries have been evaluated and their impact on etch rates and selectivities for spacer applications have been evaluated. Surface analysis techniques such as XPS and FTIR have been applied in conjunction with OES analysis of the plasma to study the etch mechanisms leading to the observed etch rates. Fundamental differences in etch mechanism were found for different etch gas chemistries.

We observed that during conventional spacer processes, very little difference in plasma polymer deposition onto the respective substrates could be noted. A successful SiN spacer process was rather facilitated by a Si etch process that was selective to SiO₂, where excess oxidation lead to a conversion of Si to SiO₂. This also means that the etch rates of the SiN are limited by the simultaneous oxidation of the same. A potential solution to overcome this limitation would be to control the etch rate by polymer thickness, similar to high selectivity SiO₂ etching. An evaluation of this approach has yielded similar results as the general etch mechanism proposed by Schaepkens et al.[1] [#_ftn1] A novel etch chemistry was also evaluated that enables a different etch mechanism that cannot be described by the general model. The impact of the described mechanisms on actual CMOS devices will be discussed in detail.