AVS1997 Session TF-TuA: ULSI Interconnects and Metallization - II

Tuesday, October 21, 1997 2:00 PM in Room B1/2

Tuesday Afternoon

Start	Invited?	Item
2:00 PM	Invited	TF-TuA-1 Low Temperature Chemical Vapor Deposition of Binary Nitrides for Emerging Computer Chip Metallization A.E. Kaloyeros, J.E. Kelsey, X. Chen, L. Xian, T. Stark (State University of New York, Albany); B. Arkles (Gelest, Inc.) As integrated circuitry moves into sub-quarter-micron device generations, significant reduction in line resistance could be achieved by replacing currently used metallization architecture, consisting of tungsten plugs and tungsten or aluminum interconnects, with fully integrated aluminum or copper metallization schemes. A major problem in the realization of the structurally stable metallization architectures is the identification of appropriate diffusion barrier/adhesion promoter materials. Such materials must provide the performance required at increasingly thinner liners to maximize space availability for the actual conductor in the continuously shrinking device structures. Tantalum (Ta) and tungsten (W) based nitrides present a promising solution. They are known to be highly refractory, stable to extremely high temperatures, and inert to reaction with copper and aluminum. Their desirability is partly based on the expectation that Ta and W are heavier (larger) ions than Ti, and accordingly their alloys should provide improved diffusion barrier performance at reduced liner thicknesses in comparison with those of Ti alloys. Our work, accordingly, has focused on the development of low-temperature (<400oC) CVD processes for the growth of ultrathin (<250Å) films of Ta and W nitrides for such applications. The processes employ simple inorganic or organometallic Ta and W sources. This paper presents progress to-date in the identification and optimization of thermal CVD processes for the growth of TaN_x and WN_x, including data from microchemical and microstructural analyses as well as conformality in sub-quarter-micron device structures.
2:40 PM		TF-TuA-3 Fast Optimization of Titanium Nitride Barriers. M. El-Ghor, M.M. IslamRaja (Texas Instruments Inc.) Titanium Nitride (TiN) has become the material of choice for contact/via barrier applications. A good barrier layer must exhibit good step coverage to achieve void free plug formation and adequate barrier thickness at the bottom of the contact/via, good diffusion barrier properties, inertness and low reactivity with adjacent materials during the thermal cycles during subsequent thermal cycles, and acceptable electrical properties such as low resistivity, low contact/via resistance and low junction leakage. Optimization of the TiN barrier is required to minimize the resistance while maintaining the reliability of the contact/via. In order to achieve this we need to minimize the TiN thickness as TiN is more resistive than the contact/via fill material (tungsten, aluminum, copper). Thinner TiN also leads to better via fill as it results in a smaller effective aspect ratio. The minimum TiN thickness is determined by the requirements for an effective barrier and the process control. Very thin films may not be continuous and/or reproducible and may be porous to the adjacent materials. A physically based model and profile simulation tool were used to optimize the thickness of the CVD TiN barriers for 0.3 µm tungsten via plugs. The use of physically based models and simulation tool significantly reduced the development cost and time. Experiments were performed using the optimum conditions to validate the predicted results. We had first pass success; the first lot we processed gave results as predicted. This optimization methodology resulted in a 40% reduction in the mean via resistance and smaller standard deviation of the via resistance without any degradation in the reliability of the vias. Although only results for via plugs have been shown in this paper, the same methodology is also being used to rapidly develop complete interconnect systems.
3:00 PM		TF-TuA-4 Nucleation of DMAH-Sourced CVD Aluminum on PVD and CVD TiN_x and PVD Ti-W B.R. Rogers (Motorola, Inc.); D. Yang, R. Jonnalagadda, T.S. Cale (Arizona State University) Chemical vapor deposited(CVD) aluminum is an attractive alternative to replace CVD tungsten for filling contact and via holes in VLSI and ULSI devices. However, the extremely rough surfaces of the CVD aluminum films currently prevent their use in microelectronics processes. Rough surfaces cause at least two problems in microelectronics processing. First, light scattering from a rough metal surface can prevent the alignment keys from being seen by the aligner, preventing computer controlled alignment of mask layers. More importantly, high points on rough films can grow together prematurely in high aspect ratio features, leaving voids in structures that were supposed to be filled. Previous workers have shown that the roughness of CVD aluminum films depend on the surfaces on which they were deposited¹, ². The work presented here tests the hypothesis that the dependence of a CVD aluminum film's surface roughness on the layer on which it was deposited is due to differences in the nucleation step of the depositions. Data describing CVD aluminum nucleation on CVD and reactive ion sputtered (RIS) TiN and sputtered Ti-W films are presented and discussed. Surface characteristics of the barrier films are tied to the respective CVD aluminum nucleation density, determined by field emission scanning electron microscopy (FESEM), and nuclei size distributions, determined using FESEM and atomic force microscopy (AFM) images. The possibility of controlling a CVD aluminum film's surface roughness by tailoring the barrier `s surface characteristics to optimized aluminum nucleation is also discussed. ¹K. I. Lee, Y. S. Kim and S. K. Joo, "Evolution of Surfac and Thin Film Microstructure", ed. by H. A. Atwater, E. Chason, M. H. Grabow and M. B. Lagally (Mat. Res. Soc., Pittsburgh, 1993). ²A. Kobayashi, A. Sekiguchi, O. Okada, N., Hosokawa, K. Sugai, S., Kishida, H. Okabayaski, T. Shinzawa, T. Yako and H. Kadokura, Electronics and Comm. in Japan, Part 2, vol. 78, 50 (1995)
3:20 PM		TF-TuA-5 Texture and Surface Morphology Improvement of Al by Two-Stage CVD and its Integration in an Al Plug-Interconnect Scheme for sub 0.25 micron Metallization. M. Naik, T. Guo, L.Y. Chen, R. Mosely, I. Beinglass, F. Chen (Applied Materials Inc.) Aluminum plug and interconnect offers the advantages of reduced process complexity, lower cost, and superior electrical performance compared to W technology for sub 0.35 micron design rule for IC$B!G(Bs. Aluminum films deposited by CVD from Dimethylaluminumhydride(DMAH) using a conventional single deposition stage process exhibited rough morphology, low reflectivity, and poor (111) texture with defects and voids. Good (111) texture is desirable for electromigration resistance, while films with smooth morphology ease integration with lithography and etch. Texture, morphology, reflectivity and composition were improved by a novel CVD process where the Al film is deposited in two stages, a seeding stage, and a bulk deposition stage separated by 30-45s. In the seeding stage which occurs within 5-10s of wafer introduction to the chamber, the wafer is exposed to a short burst(5-10s) of DMAH. The DMAH flow is then stopped. After allowing time to stabilize pressure and equilibrate wafer temperature, another deposition step follows. Here, the Al film is grown to the required thickness. The 300-800 Angstrom Al deposited in the seeding stage acts as the nucleation layer for the bulk film growth. The two stage deposition improves the reflectivity of CVD Al on titanium from less than 160 percent to greater than 210 percent for a 3500 Angstrom thick film. Also, a significantly lower rate of decrease of reflectivity with increase in Al thickness was realized. X-ray rocking curves show a decrease in the full width at half maximum of the Al(111) peak from 5.1 to 2.6, indicating significantly improved texture. SIMS analysis of Al shows a decrease in carbon content. The two stage deposition for CVD Al was integrated without a vacuum break with Ti and PVD AlCu to a.)develop sub 0.25 micron design rule via fill capability, and b.) dope the CVD Al with Copper. We will present TEM, SEM, XRD and SIMS data to show morphology and texture improvement with Cu doping of CVD Al and excellent via fill characteristics.
3:40 PM		TF-TuA-6 An Experimental Study of the Effects of Substrate Temperature Ramping on CVD-Al Film Properties R. Jonnalagadda, D. Yang, T.S. Cale (Arizona State University); J.T. Hillman, R.F. Foster (Materials Research Corporation); B.R. Rogers (Motorola, Inc.) One of the problems with some Al films grown by CVD processes is their rough surface morphology. The roughness of the films is believed to be a result of the slow rate of nucleation of aluminum on the substrates relative to the rate of growth¹. Since the kinetic barrier towards steady state growth is usually lower than the barrier towards initial nucleation¹, we designed experiments to study the effects of programmed substrate temperature ramping on nucleation density, growth rate, surface roughness, film crystal orientation and resistivity for the CVD of TIBA sourced Al on Si(100) and TiN_x coated silicon wafers. In this paper we present the results for; depositions in which the substrate temperature was kept constant at 573 K and depositions in which the substrate temperature was ramped up from 523 K, down from 723 K or down from 673 K, to a base temperature of 573 K. We also present results from experiments in which the precursor flow was started and stopped (pulsed) for a short time at higher temperatures on TiN wafers, followed by temperature ramp down and depositions at a lower (constant) base temperature 573 K. Four substrate temperature ramp down trajectories were used for the pulsed precursor flow experiments. The temperature ramp up rate was 100 K/min and the ramp down rate was -200 K/min for all the experiments. Our results show that films deposited in the pulsed flow experiments in the temperature trajectory of 673 K to 573 K on TiN wafers had a higher nucleation density, higher Al(111) texturing, lower surface roughness and lower resistivity (within 3 % of that of bulk aluminum-2.7 µOHM-cm), than films deposited in all other experiments on TiN wafers. The films deposited on Si(100) during the substrate temperature ramp down from 673 K to 573 K had a dominant Al(200) texturing. ¹1. M. G. Simmonds and W. L. Gladfelter in T. Kodas and M. Hampden-Smith (ed.), The Chemistry of Metal CVD, VCH, Weinheim, 1994, p. 45.
4:00 PM		TF-TuA-7 Growth and Coalescence of Al Nuclei during CVD and PVD N.M. Russell, A. Konecni, J.D. Luttmer (Texas Instruments) It has recently been demonstrated that deposition of a thin CVD Al liner prior to PVD Al reflow enables the filling of high aspect ratio vias at lower temperatures than previously possible. The desired morphology for this thin (300-700 Å) aluminum liner is a smooth and continuous film, which provides a diffusion path for PVD-deposited material to fill the via. The Volmer-Weber growth mode of CVD Al on technologically-relevant substrates dictates that some minimum amount of aluminum must be deposited before the nuclei coalesce to form a continuous film. We have investigated the initial stages (50 to 600 Å) of PVD and CVD Al deposition on CVD TiN and PVD Ti/TiN layers deposited on oxide-covered silicon wafers in a vacuum cluster tool. Nucleus size distributions obtained from plan-view SEM images indicate that the morphology of CVD-Al evolves differently than that of PVD-Al deposited at 200 °C with the same growth rate, which we attribute to the higher reaction rate of dimethylaluminum hydride on existing nuclei relative to the incubation of new nuclei. With a 60 °C decrease in growth temperature, the relative rate of reaction on the aluminum clusters drops more rapidly than the rate of formation of fresh nuclei on the TiN surface, and a high density of small nuclei result that coalesce into a smooth, continuous film after 200-300 Å of deposition, compared to 400-600 Å with a rougher morphology at 200 °C, as determined by AFM. PVD Al deposited with the same growth rate as the CVD Al at these two temperatures shows some influence of coarsening via surface diffusion, but the effect of temperature over this range is much smaller than that observed for CVD Al deposition.
4:20 PM		TF-TuA-8 Aluminum CVD from Dimethylaluminumhydride-Dimethylethylamine (DMAH-DMEA): Relationship between Growth Mechanism and Film Morphology. C.J. Taylor, J.T. Roberts, W.L. Gladfelter (University of Minnesota) Aluminum is an important component of many microelectronic devices. Chemical vapor deposition (CVD) is a promising alternative to conventional physical vapor deposition (PVD) methods for aluminum deposition. Historically, aluminum CVD has been plagued by problems such as low and uneven nucleation densities, which results in the formation of unacceptably rough films. In an attempt to understand the origin of film quality in CVD, the growth of aluminum films from dimethylaluminumhydride-dimethylethylamine (DMAH-DMEA) on GaAs(100) and sputtered TiN/Si(100) surfaces was studied. Significantly, it was observed that film microstructure, as measured by x-ray diffraction (XRD) methods) varies with deposition temperature. At low temperatures (<500K), the XRD patterns of films deposited by CVD and PVD are qualitatively different. At higher temperatures there is no apparent difference between films deposited by CVD and PVD. Growth rate measurements show that growth below 500 K is limited by the precursor decomposition rate, while above 500 K it is limited by precursor flux to the growth substrate. The results therefore suggest that the CVD decomposition mechanism has an effect on film microstructure.
4:40 PM		TF-TuA-9 Integrated CVD-PVD Metallization on High-Vacuum Cluster Tools. A. Tolia, T. Guo, R. Mosely, F. Chen (Applied Materials Inc.) Metallization solutions for the sub 0.35 µ m regime will require integration of heretofore separate technologies. Applied Materials has recently announced two products that combine Metal CVD and PVD on an integrated cluster platform, the Endura VHP Metallization Tool. One configuration of this technology is for Al planarization using the Cool Al^TM sequence. This process utilizes a combination of CVD Al and PVD Al for plug fill and IMP Ti and CVD TiN as liner/barrier. Another application is using IMP Ti and CVD TiN as liners for tungsten plugs. Integrating the CVD chambers onto the Endura platform offers several key advantages for process sequence integration. For the Cool Al^TM process, the integrated sequence results in epitaxial growth of PVD Al film on top of the CVD Al, while non-integrated sequences with air break after the CVD Al results in an oxidized interfacial layer. Consequently, PVD Al reflow in contacts and vias lined with CVD Al is much more facile when the two processes are integrated on the same vacuum cluster tool. Additionally, the contact/via resistance of Ti/TiN stacks is also improved when there is no air break between IMP Ti and CVD TiN. The CVD processes typically operate at much higher pressure than their PVD counterparts (1-25 Torr vs. 1-10 mTorr) and use chemically reactive precursors. The wafer transfer chamber and PVD chambers on the Endura are maintained at a base pressure less than 5 x 10^-8 Torr. As a result there is some concern about potential contamination of the high vacuum transfer chamber as well PVD process chambers and targets on integrated tools. This paper reports for the first time a detailed study to examine the effects of integrating CVD chambers on the high-vacuum Endura system. The hardware configuration will be discussed in some detail. A detailed gas-phase characterization of all the process chambers using Residual Gas Analyzers has been performed. Additionally, the effect of the CVD chamber integration on PVD film purity has been studied by a comprehensive chemical and structural analysis using SIMS, XPS and XRD. The impact on Al and Ti target purity has also been evaluated using the X-ray rocking curves of the Al and Ti films as a measure of target contamination. In general, it was found that the integration of CVD chambers on the high vacuum Endura does not appear to cause any significant deterioration of the PVD films or process chambers.
5:00 PM		TF-TuA-10 Submicron Contacts for Electrical Characterisation of Semiconducting WS₂ Thin Films. C. Ballif, M. Regula (Ecole Polytechnique Fédérale de Lausanne, Switzerland); F. Burmeister, C. Schäfle, T. Matthes (Universität Konstanz, Germany); F. Lévy (Ecole Polytechnique Fédérale de Lausanne, Switzerland) We report an original method to characterise the electronic properties of polycrystalline semiconducting WS₂ thin films. Deposition of submicron gold contacts on the films, and the use of an atomic force microscope (AFM) with a conductive tip, are combined in order to explore the possibility to prepare metal/semiconductor junctions on the films. The WS₂ films are prepared by a sputtering/annealing process ¹. They are p-type with large (1-5µm) flat WS₂ crystallites. Monolayers of hexagonally closed packed latex spheres (0.8-3µm diameter) are prepared and transferred² onto the WS₂ films . After gold evaporation and removal of the latex spheres by ultrasonic bath, the WS₂ film is covered with a lattice of triangular gold electrodes, whose sizes range from 100 to 500nm depending on the size of the latex spheres. The electrical properties of each contact established between the triangle and the WS₂ film are investigated using the electrical AFM set-up. The major advantage of the method, compared to direct STM or AFM measurements, is to measure a realistic metal/semiconductor interface, avoiding the usual lack of information on the tip-sample geometry and interaction. In principle, it opens the way to a large variety of quantitative opto-electrical measurements at a scale which can range down to some tens of nanometers. The method is a powerful tool to study local properties of polycrystalline films, multi-phase or inhomogenous materials. In the case of the p-type WS₂ thin films, linear I-V characteristics are obtained on gold triangles in contact with grain edges. This indicate a high level of doping or degeneracy of the semiconductor at grain edges. The triangles which are deposited on flat WS₂ crystallites and do not touch grain edges, form Schottky barriers with the underlying grains, and I-V curves typical of metal/p-type semiconductor junctions are obtained. ¹C. Ballif., M.Regula, P.E. Schmidt, R. Sanjinés M. Rems˜kar, and F. Lévy, App. Phys. A 62, 543-546 (1996). ²F. Burmeister, C. Schäfle, T. Matthes, M. Böhmish, J. Boneberg, P.Leiderer, to be published in Langmuir